Test: Digital Electronics - 4

Question 1

For an N bit ADC, the percentage resolution is [1/2^N - 1)] 100.

Accepted Answer

True

Answer

False

Question 2

Dynamic memory cells are constructed using

Accepted Answer

MOSFETs

Answer

FETs

Answer

Transistors

Answer

Flip flops

Question 3

Commercial ECL gates use two ground lines and one negative supply to

Accepted Answer

eliminate the effect of power line glitches on the biasing circuit

Answer

reduce power consumption

Answer

increase fan out

Answer

reduce loading effect

Question 4

Which of the following is incorrect?

Accepted Answer

(8)₁₆ = (8)₈

Answer

(5)₁₆ = (5)₈

Answer

(8)₂ = (2)₁₀

Answer

(2)₁₆ = (2)₁₀

Question 5

A 3 stage Johnson counter (ring) shown in figure is clocked at a constant frequency of fc from the starting state of Q₀ Q₁ Q₂ = 101. The frequency of output Q₀ Q₁ Q₂ will be

Accepted Answer

Answer

Answer

Answer

Question 6

A depletion type NMOS is operated in enhancement mode. V_p = - 4 volts. For V_GS = + 3 volts as V_DS is increased, I_D becomes nearly constant when V_ps equals

Accepted Answer

7 volts

Answer

1 volt

Answer

3 volts

Answer

4 volt

Question 7

A number is expressed in binary 2's complement as 10011 decimal equivalent value is

Accepted Answer

-13

Answer

19

Answer

13

Answer

-19

Question 8

Which one of the following is D/A conversion technique?

Accepted Answer

Weighted resistor

Answer

Successive approximation

Answer

Dual slope

Answer

Single slope

Question 9

Assuming accumulator contain A 64 and the carry is set (1). What will accumulator (A) and carry (CY) contain after ANA A?

Accepted Answer

A 6 H, 0

Answer

A 6 H, 1

Answer

00 H, 0

Answer

00 H, 1

Question 10

In INHIBIT operation

Accepted Answer

output is 0 when blocking input is 1

Answer

output is 1 when both inputs are 0

Answer

output is 0 when blocking input is 0

Answer

output is 1 when blocking input is either 0 or 1

Question 11

The product of which of the following gives the figure of merit of a logic family?

Accepted Answer

Propagation delay time and power dissipation

Answer

Gain and bandwidth

Answer

Fan-out and propagation delay time

Answer

Noise margin and power dissipation

Question 12

A JK flip flop can be converted to D flip flop by

Accepted Answer

Connecting J terminal to D and K terminal to D through an inverter

Answer

Connecting both J and K terminals to D

Answer

Connecting J terminal to D and leaving K open

Answer

Connecting K terminal to D and leaving J open

Question 13

In a 4 bit parallel in parallel out shift register A = 1, B = 1, C = 0, D = 1. The data output after 3 clock pulses is

Accepted Answer

1101

Answer

1001

Answer

0101

Answer

0001

Question 14

Assertion (A): A 4 input variable logic circuit can be implemented using a 8 : 1 multiplexer.

Reason (R): When a multiplexer is used as a logic function generator, the logic design is simple.

Accepted Answer

Both A and R are correct but R is not correct explanation of A

Answer

Both A and R are correct and R is correct explanation of A

Answer

A is true, R is false

Answer

A is false, R is true

Question 15

A 6 MHz channel is used by a digital signalling system initializing four-level signals. The maximum possible transmission rate is

Accepted Answer

6M bands/s

Answer

12M bands/s

Answer

6 M bits/s

Answer

12M bits/s

Question 16

Data can be changed from spatial code to temporal code and vice-versa by using

Accepted Answer

shift Register

Answer

ADC and DAC

Answer

synchronous counter

Answer

timers

Question 17

Precisely 1 K byte means

Accepted Answer

1024 bits

Answer

1000 bits

Answer

1012 bits

Answer

1020bits

Question 18

In 8156, the lower times byte is addressed with 24 H, and the upper times byte with

Accepted Answer

25 H

Answer

20 H

Answer

23 H

Answer

24 H

Question 19

In the CMOS inverter

Accepted Answer

one is enhancement type and other depletion type

Answer

one transistor is N channel and the other P channel

Answer

both are N channel with one enhancement and the other depletion type

Answer

none

Question 20

Which of the following is incorrect?

Accepted Answer

(8)₈ + (2)₈ = (11)₈

Answer

11101 + 10 = 11111

Answer

(8)₁₆ + (7)₁₆ = E

Answer

All of them are incorrect

Question 21

Which one of the following is used to change data from spatial code to temporal code?

Accepted Answer

Shift register

Answer

Counter

Answer

A/D converters

Answer

Combinational circuits

Question 22

Which of the following needs DC forward voltage to emit light?

Accepted Answer

LED

Answer

LCD

Answer

Both LED as well as LCD

Answer

None of the above

Question 23

If a microcomputer has a 64 K memory; what is the hexadecimal notations for the last memory location?

Accepted Answer

FFFF

Answer

1111

Answer

1A1A

Answer

EEEF

Question 24

In the given figure shows a 3 bit shift register using TTL flip flops. Initially all the flip flops are set to 0 state. After 8 clock pulses

Accepted Answer

A = 1, B = 1, C = 1

Answer

A = 1, B = 1, C = 0

Answer

A = 0, B = 1, C = 1

Answer

A = 0, B = 0, C = 1

Question 25

Recommended fanout for ECL is

Accepted Answer

25

Answer

5

Answer

10

Answer

15

Digital Electronics - 4 - Free MCQ Practice Test with solutions, GATE EE

MCQ Practice Test & Solutions: Test: Digital Electronics - 4 (25 Questions)

For an N bit ADC, the percentage resolution is [1/2^N - 1)] 100.

Dynamic memory cells are constructed using

Commercial ECL gates use two ground lines and one negative supply to

Which of the following is incorrect?

A 3 stage Johnson counter (ring) shown in figure is clocked at a constant frequency of fc from the starting state of Q₀ Q₁ Q₂ = 101. The frequency of output Q₀ Q₁ Q₂ will be

A depletion type NMOS is operated in enhancement mode. V_p = - 4 volts. For V_GS = + 3 volts as V_DS is increased, I_D becomes nearly constant when V_ps equals

A number is expressed in binary 2's complement as 10011 decimal equivalent value is

Which one of the following is D/A conversion technique?

Assuming accumulator contain A 64 and the carry is set (1). What will accumulator (A) and carry (CY) contain after ANA A?

In INHIBIT operation

The product of which of the following gives the figure of merit of a logic family?

A JK flip flop can be converted to D flip flop by

In a 4 bit parallel in parallel out shift register A = 1, B = 1, C = 0, D = 1. The data output after 3 clock pulses is

Assertion (A): A 4 input variable logic circuit can be implemented using a 8 : 1 multiplexer.
Reason (R): When a multiplexer is used as a logic function generator, the logic design is simple.

A 6 MHz channel is used by a digital signalling system initializing four-level signals. The maximum possible transmission rate is

Data can be changed from spatial code to temporal code and vice-versa by using

Precisely 1 K byte means

In 8156, the lower times byte is addressed with 24 H, and the upper times byte with

In the CMOS inverter

Which of the following is incorrect?

Which one of the following is used to change data from spatial code to temporal code?

Which of the following needs DC forward voltage to emit light?

If a microcomputer has a 64 K memory; what is the hexadecimal notations for the last memory location?

In the given figure shows a 3 bit shift register using TTL flip flops. Initially all the flip flops are set to 0 state. After 8 clock pulses

Recommended fanout for ECL is

Digital Electronics

Digital Electronics

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Digital Electronics - 4 - Free MCQ Practice Test with solutions, GATE EE

MCQ Practice Test & Solutions: Test: Digital Electronics - 4 (25 Questions)

For an N bit ADC, the percentage resolution is [1/2N - 1)] 100.

Dynamic memory cells are constructed using

Commercial ECL gates use two ground lines and one negative supply to

Which of the following is incorrect?

A 3 stage Johnson counter (ring) shown in figure is clocked at a constant frequency of fc from the starting state of Q0 Q1 Q2 = 101. The frequency of output Q0 Q1 Q2 will be

A depletion type NMOS is operated in enhancement mode. Vp = - 4 volts. For VGS = + 3 volts as VDS is increased, ID becomes nearly constant when Vps equals

A number is expressed in binary 2's complement as 10011 decimal equivalent value is

Which one of the following is D/A conversion technique?

Assuming accumulator contain A 64 and the carry is set (1). What will accumulator (A) and carry (CY) contain after ANA A?

In INHIBIT operation

The product of which of the following gives the figure of merit of a logic family?

A JK flip flop can be converted to D flip flop by

In a 4 bit parallel in parallel out shift register A = 1, B = 1, C = 0, D = 1. The data output after 3 clock pulses is

Assertion (A): A 4 input variable logic circuit can be implemented using a 8 : 1 multiplexer.Reason (R): When a multiplexer is used as a logic function generator, the logic design is simple.

A 6 MHz channel is used by a digital signalling system initializing four-level signals. The maximum possible transmission rate is

Data can be changed from spatial code to temporal code and vice-versa by using

Precisely 1 K byte means

In 8156, the lower times byte is addressed with 24 H, and the upper times byte with

In the CMOS inverter

Which of the following is incorrect?

Which one of the following is used to change data from spatial code to temporal code?

Which of the following needs DC forward voltage to emit light?

If a microcomputer has a 64 K memory; what is the hexadecimal notations for the last memory location?

In the given figure shows a 3 bit shift register using TTL flip flops. Initially all the flip flops are set to 0 state. After 8 clock pulses

Recommended fanout for ECL is

Digital Electronics

Digital Electronics

Top Courses for Electrical Engineering (EE)

About this Electrical Engineering (EE) Practice Test

Explore more Electrical Engineering (EE) Study Resources

For an N bit ADC, the percentage resolution is [1/2^N - 1)] 100.

A 3 stage Johnson counter (ring) shown in figure is clocked at a constant frequency of fc from the starting state of Q₀ Q₁ Q₂ = 101. The frequency of output Q₀ Q₁ Q₂ will be

A depletion type NMOS is operated in enhancement mode. V_p = - 4 volts. For V_GS = + 3 volts as V_DS is increased, I_D becomes nearly constant when V_ps equals

Assertion (A): A 4 input variable logic circuit can be implemented using a 8 : 1 multiplexer.
Reason (R): When a multiplexer is used as a logic function generator, the logic design is simple.