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Computer Science Engineering (CSE) Exam  >  Computer Science Engineering (CSE) Tests  >  Test: RISC Processor - Computer Science Engineering (CSE) MCQ

Test: RISC Processor - Computer Science Engineering (CSE) MCQ


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15 Questions MCQ Test - Test: RISC Processor

Test: RISC Processor for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Test: RISC Processor questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: RISC Processor MCQs are made for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: RISC Processor below.
Solutions of Test: RISC Processor questions in English are available as part of our course for Computer Science Engineering (CSE) & Test: RISC Processor solutions in Hindi for Computer Science Engineering (CSE) course. Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free. Attempt Test: RISC Processor | 15 questions in 25 minutes | Mock test for Computer Science Engineering (CSE) preparation | Free important questions MCQ to study for Computer Science Engineering (CSE) Exam | Download free PDF with solutions
Test: RISC Processor - Question 1
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Which are the processors based on RISC?

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Explanation: SPARC and MIPS processors are the first generation processors of RISC architecture.

Test: RISC Processor - Question 2
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What is 80/20 rule?

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Explanation: 80% of instructions are generated and only 20% of the instruction set is executed that is, by simplifying the instructions, the performance of the processor can be increased which lead to the formation of RISC that is reduced instruction set computing.

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Test: RISC Processor - Question 3
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Which of the architecture is more complex?

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Explanation: SPARC have RISC architecture which has a simple instruction set but MC68020, MC68030, 8086 have CISC architecture which is more complex than CISC.

Test: RISC Processor - Question 4
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Which is the first company who defined RISC architecture?
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Explanation: In 1970s IBM identified RISC architecture.

Test: RISC Processor - Question 5
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Which of the following processors execute its instruction in a single cycle?
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Explanation: MIPS R2000 possess RISC architecture in which the processor executes its instruction in a single clock cycle and also synthesize complex operations from the same reduced instruction set.

Test: RISC Processor - Question 6
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 How is memory accessed in RISC architecture?
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Explanation: The data of memory address is loaded into a register and manipulated, its contents are written out to the main memory.

Test: RISC Processor - Question 7
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Which of the following has a Harvard architecture?
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Explanation: PIC follows Harvard architecture in which the external bus architecture consist of separate buses for instruction and data whereas SSEM, EDSAC, CSIRAC are stored program architecture.

Test: RISC Processor - Question 8
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 Which of the following statements are true for von Neumann architecture?
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Explanation: von Neumann architecture shares bus between program memory and data memory whereas Harvard architecture have a separate bus for program memory and data memory.

Test: RISC Processor - Question 9
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What is CAM stands for?
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Explanation: Non-von Neumann architecture is based on content-addressable memory.

Test: RISC Processor - Question 10
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Which of the following processors uses Harvard architecture?
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Explanation: It is a digital signal processor which have small and highly optimized audio or video processing signals. It possesses multiple parallel data bus.

Test: RISC Processor - Question 11
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Which company further developed the study of RISC architecture?
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Explanation: The University of Berkeley and Stanford university provides the basic architecture model of RISC.

Test: RISC Processor - Question 12
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 Princeton architecture is also known as
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Explanation: The von Neumann architecture is also known as von Neumann model or Princeton architecture.

Test: RISC Processor - Question 13
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Who coined the term RISC?
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Explanation: David Patterson of Berkeley university coined the term RISC whereas Michael J Flynn who first views RISC.

Test: RISC Processor - Question 14
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Which of the following is an 8-bit RISC Harvard architecture?
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Explanation: AVR is an 8-bit RISC architecture developed by Atmel. Zilog80, 8051, Motorola 6800 are having CISC architectures.

Test: RISC Processor - Question 15
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Which of the following processors has CISC architecture?
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Explanation: Zilog80 have CISC architecture whereas AVR, Atmel and blackfin possess RISC architecture.

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