Test: DRAM Refreshing Techniques - Computer Science Engineering (CSE) MCQ

Explanation: The DRAM needs to be periodically refreshed and the very basic technique is a special refresh cycle, during these cycles no other access is permitted. The whole chip is refreshed within a particular time period otherwise, the data will be lost.

Explanation: The time required for refreshing the whole chip is known as refresh time. The number of access needed to complete refresh is called as the number of cycles. The number of cycles divided by the refresh time gives the refresh rate

Explanation: There are two refresh rates used in common. They are standard refresh rate of 15.6 microseconds and 125 microseconds which the extended form.

Explanation: Each of the refresh cycles is approximately as twice as the length of the normal access, for example, a 70ns DRAM has a refresh cycle time of 130ns.

Explanation: When the refresh cycle in a DRAM is running, it will not access data, so the processor will have to wait for its data. This arises some timing issues.

Explanation: A 4M by 1 DRAM have 1024 refresh cycles. Bursting delay will be 0.2ms that is, the worst case delay is 1024 times larger than that of the single refresh cycle. The distributed delay is about 170ns.

Explanation: Most of the system uses the distributed method and depending on the size of the time critical code, the number of refresh cycles can be calculated.

Explanation: The software refresh performs the action by using a routine to periodically cycle through the memory and refreshes. It uses a timer in the program generating an interrupt. This interrupt performs the refreshing part in the DRAM.

Explanation: Debugging in software refresh is very difficult to perform because they may stop the refreshing and if the refreshing is stopped, the contents get lost.

Explanation: CBR that is, CAS before RAS refresh is the one which is commonly used. It has low power consumption quality because it does not have address bus and the buffers can be switched off. It is worked by using an internal address counter which is stored on the memory chip itself and this can be incremented periodically.

Explanation: The row address is placed on the address bus and the column address is held off which generates the recycle address. The address generation is done by an external hardware controller.

Explanation: The Apple II personal computer have a particular memory configuration, periodically the DRAM gets blocked and is used for video memory accessing to update the screen which can refresh the DRAM.

Explanation: CBR works by an internal address counter which is periodically incremented. The mechanism is based on CAS before RAS. Each time when RAS is asserted, the refresh cycle performs and the counter is incremented.

Explanation: In the hidden refresh, the refresh cycle is added to the end of a normal read cycle. The RAS signal goes high and is then asserted low. In the end of the read cycle, the CAS is still asserted. This is similar to the CBR mechanism, that is, toggling of RAS signal at the end of the read cycle starts a CBR refresh cycle.

Explanation: The maximum time interval between refresh cycle is standardized by JEDEC, Joint Electron Device Engineering Council which is an independent semiconductor engineering trade organization. This standardized JEDEC in DRAM is specified in the manufacturer’s chip specification.