Test: Cache Memory & Size of Cache - Computer Science Engineering (CSE) MCQ

Explanation: The cache memory is a small random access memory which is faster than a normal RAM. It has a direct connection with the CPU otherwise, there will be a separate bus for accessing data. The processor will check whether the copy of the required data is present in the cache memory if so it will access the data from the cache memory.

Explanation: The proportion of accesses of data that forms the cache hit, which measures the effectiveness of the cache memory.

Explanation: The size of the cache increases, a large amount of data can be stored, which can access more data which in turn increases the hit rate of the cache memory.

Explanation: The translation lookaside buffer is common cache memory seen in almost all CPUs and desktops which are a part of the memory management unit. It can improve the virtual address translation speed.

Explanation: The set associativity is a criterion which describes the number of cache entries which could possibly contain the required data.

Explanation: The 8086 processor have a 64 Kbytes cache, beyond this size, the cost will be extremely high.

Explanation: The direct mapped cache only have one possibility to fetch data whereas a two-way system, there are two possibilities, for a three-way system, there are three possibilities and so on. It is also known as the one-way set associative cache.

Explanation: The direct mapped cache has the advantage of allowing a simple and fast speculative execution.

Explanation: The cache line refers to the number of consecutive bytes which are associated with each cache entry. The data is transferred between the memory and the cache in a particular size which is called cache line.

Explanation: The cache performance is completely dependent on the system and software. In software, the processor checks out each loop and if a duplicate is found in the cache memory, immediately it is accessed.

Explanation: The cache memory operation is based on the address tag, that is, the processor generates the address which is provided to the cache and this cache stores its data with an address tag. The tag is compared with the address, if they did not match, the next tag is checked. If they match, a cache hit occurs, the data is passed to the processor. So the basic elements required is a memory array, comparator, and a counter.

Explanation: There is four classification based on the tag or index address corresponds to a virtual or physical address. They are PIPT, VIVT, PIVT, VIPT that is, physically indexed physically tagged, virtually indexed virtually tagged, physically indexed virtually tagged, virtually indexed physically tagged respectively.

Explanation: A fully associative cache have a comparator for each entry so that all the entries can be tested simultaneously.

Explanation: The major disadvantage of the fully associative cache is the amount of hardware needed for the comparison increases in proportion to the cache size and hence, limits the fully associative cache.

Explanation: The direct mapping cache have only one comparator so that only one location possibly have all the data irrespective of the cache size.

Explanation: The direct mapping cache organization is simple from the hardware design aspects but it is inefficient in the software viewpoint.

Explanation: The index mechanism splits the external memory storage into a series of memory pages in which each page is the same size of the cache. Each page is mapped to the cache so that each page can have its own location in the cache.

Explanation: Only one data can be accessed in direct mapping that is, if one word is accessed at a time, all other words are discarded at the same time. This is known as bus thrashing which can be solved by splitting up the caches so there are 2,4,..n possible entries available. The major advantage of the set associative cache is its capability to prevent the bus thrashing at the expense of hardware.

Explanation: The burst fill mode of cache mapping have a sequential nature of executing instructions and data access. The instruction fetches and execution accesses to sequential memory locations until it has a jump instruction or a branch instruction. This kind of cache mapping is seen in MC68030 processor.

Explanation: The cache memory uses either a physical address or logical address for its tag data. For a logical cache, the tag refers to a logical address and for a physical cache, the tag refers to the physical address.

Explanation: In the physical cache, the data is preserved within the cache because it does not flush out during the context switching but on the other hand, the logical cache flushes out the data and clear it during a context switching.

Explanation: The physical address access the data through the memory management unit which causes a delay.

Explanation: The physical cache is more efficient and can provide the cache coherency problem solved and MMU delay are kept to a minimum. PowerPC is an example for this advantage.

Explanation: The Intel 80486DX processor has a unified cache. Similarly, Motorola MPC601PC also uses the unified cache. The unified cache has the same mechanism to store both data and instructions.

Explanation: The Harvard cache have a separate cache for the data and the instruction whereas the unified cache has a same cache for the data and instructions.