Test: Segmentation & Paging - Computer Science Engineering (CSE) MCQ

Explanation: The dirty bit is said to be set, if the processor modifies its memory. This bit indicates that the associative set of blocks regarding the memory is modified and has not yet saved to the storage.

Explanation: DEC Alpha divides its memory into 8KB pages whereas VAX is a small page which are only 512 bytes in size. PowerPC pages are normally 4 KB and ARM is having 4 KB and 64 KB pages.

Explanation: The logical address is the address generated by the CPU. It is also known as virtual address. The physical address is the address which is seen by the memory unit.

Explanation: The main memory can splits into small blocks by the method of paging and segmentation and these mechanism are possible only in protected mode.

Explanation: The address translation from the logical address to physical address partitions the main memory into different blocks which is called segmentation. Each of these blocks have a descriptor which possesses a descriptor table. So the size of every block is very important for the descriptor.

Explanation: The granularity bit controls the resolution of the segmented memory. When it is set to logic one, the resolution is 4 KB. When the granularity bit is set to logic zero, the resolution is 1 byte.

Explanation: There are two types of descriptor table used by the processor in the protected mode which are GDT and LDT, that is global descriptor table and local descriptor table respectively.

Explanation: The table indicator is a part of selector that selects which table is to be used. If the table indicator is sets to logic one, the will use the local descriptor table and if the table indicator is sets to logic zero, it will use the global descriptor table.

Explanation: The global descriptor table register is a special register which have the linear address and the size of its own GDT. Both the global descriptor table register and local descriptor table register are located in the global descriptor table.

Explanation: The paged memory management unit is used to decrease the amount of storage needed in the page tables, that is, a multi-level tree structure is used. MC68030, PowerPC, ARM 920 uses a paged memory management unit.