Test: DMA: Embedded Systems I/O - Computer Science Engineering (CSE) MCQ

Explanation: The DMA controllers or direct memory access controller provides an efficient method for transferring data from the peripheral to the memory.

Explanation: The polling and interrupt helps for data transmission for the systems which do not have DMA controller.

Explanation: The DMA controller can initiate and control the bus access between I/O devices and memory, and also between two different memory areas. Therefore, the DMA controller can act as a hardware implementation of low-level buffer filling or emptying the interrupt.

Explanation: There are three classifications for the DMA controllers based on the address capability. These are 1D, 2D and 3D.

Explanation: The 1D controller only have a single address register whereas 2D controller have two address register and 3D controller have three or more address register.

Explanation: The generic controller have several components associated with it for controlling the operation and one such is the address generator. It consists of the base address register and an auto-incrementing counter which increment the address after every transfer.

Explanation: The data bus is used for the transmission of data from the DMA controller to the destinal. The DMA controller can directly select the peripheral in some cases in which the data transfer is made from the peripheral to the memory.

Explanation: The bus requester requests the bus from the main CPU. In earlier design, the processor bus does not support the multi master system and there were no bus request signals. In such cases, the processor clock was extended.

Explanation: The interrupt signal can identify the error occurred in the DMA controller. This makes the processor to reprogram the DMA controller for a different transfer.

Explanation: The local peripheral control allows the DMA controller to select the peripheral.

Explanation: The single address model is also known as implicit model because the second address is implied and is not directly given, that is, the source address is not supplied.

Explanation: The dual address mode supports two addresses and two accesses for transferring data between a peripheral or memory and another memory location.

Explanation: The dual address mode supports two addresses and two accesses for transferring data between a peripheral or memory and another memory location, which also consumes two bus cycles and a buffer within the DMA controller to hold data temporarily

Explanation: The 1D model can implement a circular buffer which makes an automatic reset to bring the address back to the beginning.

Explanation: The 1D model of the DMA controller uses an address location and a counter to define the address sequence which are used during the DMA cycles.

Explanation: An address stride is specified which can be used for calculating the offset to the base address at the terminal of count. This address stride is used in the 2D model of the DMA controller.

Explanation: In the 2D model of the DMA controller, an address stride is specified which can be used for calculating the offset to the base address at the terminal of count.

Explanation: In the 2D model of the DMA controller, in addition to the address stride there is a count register which can be split into two, in which one register is used to specify the count for the block and the second register is used to define the total number of blocks or the bytes to be transferred.

Explanation: In the 3D model of the DMA controller, it have the ability to change the address stride automatically so that blocks of different sizes and stride can be created.

Explanation: The arbitration is used to provide priority for a multiple access. This uses a priority scheme which may offers fair priority to the one channel, or a high priority to the other channel and so on. Such condition is otherwise known as round-robin condition in which the priority is equally divided.