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Computer Science Engineering (CSE) Exam  >  Computer Science Engineering (CSE) Tests  >  Test: Implementation of DMA - Computer Science Engineering (CSE) MCQ

Test: Implementation of DMA - Computer Science Engineering (CSE) MCQ


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10 Questions MCQ Test - Test: Implementation of DMA

Test: Implementation of DMA for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Test: Implementation of DMA questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: Implementation of DMA MCQs are made for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Implementation of DMA below.
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Test: Implementation of DMA - Question 1
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 Which of the following DMA is used in the IBM PC?

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Explanation: The Intel 8237 is the DMA used in the IBM PC. 8253,8254 and 8259 are timers developed by Intel.

Test: Implementation of DMA - Question 2
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Which of the following have four transfer modes?

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Explanation: The Intel 8237 have four transfer modes. These are single mode, block transfer mode, demand mode and cascade mode.

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Test: Implementation of DMA - Question 3
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 Identify the additional transfer mode in the Intel 8237?

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Explanation: In addition to the four main transfer mode, there is a verify transfer mode which is used within the PC to create dummy addresses which is used for refreshing the DRAM.

Test: Implementation of DMA - Question 4
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 Which of the following transfer mode can refresh the DRAM memory?
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Explanation: The verify address transfer mode can generate dummy addresses which is used for the DRAM refreshing.

Test: Implementation of DMA - Question 5
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Which of the following is used for supporting the priority scheme?
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Explanation: The arbitration is used for providing priority to the DMA requests. The DMA request are simultaneously generating, so in order to avoid the errors, a priority scheme is necessary which is done by the arbitration scheme in the DMA controller.

Test: Implementation of DMA - Question 6
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 Which of the following consist of a fully programmable DMA controller of two channels?
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Explanation: The MC68300 is developed by Motorola, which consists of a two channel fully programmable DMA controller which can support high speed data transfer.

Test: Implementation of DMA - Question 7
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 Which cycle can support the burst and single transfer mode?
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Explanation: The internal cycles can be programmed to occupy the partial or complete fulfillment of the available internal bus bandwidth while the external cycles provides support to the single transfer modes and burst mode.

Test: Implementation of DMA - Question 8
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Which of the following requires its own local memory and program?
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Explanation: The DMA CPU has its own address local memory and program so that it will not harm main memory bus and it is completely isolated.

Test: Implementation of DMA - Question 9
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Which DMA is programmed with higher level software?
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Explanation: The DMA CPU is programmed with higher level software which is used to transfer the data and for processing it.

Test: Implementation of DMA - Question 10
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Which of the following combine an MC68000/MC68020 type of processor with peripheral and DMA controllers?
Detailed Solution for Test: Implementation of DMA - Question 10

Explanation: The MC68300 combines the processors along with the DMA controllers. The processors which support the MC68300 series are MC68000 or MC68020.

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