Test: RISC Exceptions - Computer Science Engineering (CSE) MCQ

Explanation: The MSR is a machine state register. When the exception is recognised, the address of the instruction and the MSR are stored in the supervisor registers while handling an exception.

Explanation: When the exception is recognised, the address of the instruction and the machine state register(MSR) are stored in the supervisor registers in the exception mode. There are two supervisor registers SRR0 and SRR1.

Explanation: When an exception is recognised, the address of the instruction and the MSR are stored in the supervisor registers and the processor moves to the supervisor mode and starts to execute the handler which is associated with the vector table. The handler examines the DSISR and FPSCR registers and carries out the required function. When it gets completed the RFI or return-from-interrupt instruction is executed.

Explanation: There are four general types of exceptions. They are synchronous precise, asynchronous precise, synchronous imprecise and asynchronous imprecise.

Explanation: The asynchronous exception is the one in which an external event causes an exception and is independent of the instruction flow. On the other hand, the synchronous exceptions are synchronised, that is, it is caused by the instruction flow.

Explanation: An imprecise exception is a catastrophic failure in which the processor cannot continue processing or allow a particular task or program to continue.

Explanation: The system reset or memory fault falls into the category of imprecise exceptions while accessing the vector table.

Explanation: The completion status can be determined by the information bits in the DSISR and FPSCR registers.

Explanation: The synchronous imprecise is usually not supported on the PowerPC architecture and also in the MPC601, MPC603 etc.

Explanation: . The PowerPC can handle the floating point exception by making use of the synchronous imprecise mode.

Explanation: The asynchronous precise type exception is used to handle the external interrupts and decrementer-caused exceptions. Both these can occur at any time within the instruction flow.

Explanation: The exception handler performs some kind of handshaking to ensure that all the interrupts are recognised.

Explanation: Two types of exceptions are associated with the asynchronous imprecise. These are system reset and machine checks.

Explanation: By doing the system reset, all the current processing are stopped and the internal registers and the memories are reset.

Explanation: The machine check exception is taken only if the ME bit of the MSR is set. If it is cleared, the processor will enter into a check stop state.

Explanation: The machine check and the system reset are two types of exceptions which are associated with the asynchronous imprecise.

Explanation: The synchronous precise exceptions provide additional priority because it is possible for an instruction to generate more than one exception.

Explanation: The system reset has the first priority then comes the machine reset, next priority moves for the instruction dependent, and the next priority is external interrupt, and last priority level goes for the decrementer interrupt.

Explanation: The EE bit in the MSR controls the external interrupts and the decrementer exceptions.

Explanation: The ME bit in the MSR controls the machine check interrupts.