Test: Introduction To VHDL - 1 - Computer Science Engineering (CSE) MCQ

Explanation: The VHDL is the hardware description language which describes the hardware whereas the C, C++ and JAVA are software languages.

Explanation: VHDL is the VHSIC(very high speed integrated circuit) hardware description language which was developed by three companies, IBM, Intermetrics and Texas Instruments and the first version of the VHDL is established in the year 1984 and later on the VHDL is standardised by the IEEE.

Explanation: The VHSIC stands for very high speed integrated chip and VHDL was designed in the context of the VHSIC, developed by the department of defence in the US.

Explanation: Each unit to be modelled in a VHDL design is known as the design entity or the VHDL entity. There are two types of ingredients are used. These are the entity declaration and the architecture declaration.

Explanation: The port map describes the connection between the entity port and the local component. The component is declared by component declaration and the entity ports are mapped with the port mapping.

Explanation: The CSA theory is proposed by Hayes and this theory is based on the systematic way of building up value sets.

Explanation: The CSA theory is proposed by Hayes. The theory is based on the systematic way of building up value sets, that is the electronics design system uses a variety of value sets, like 2, 3 etc. The goal of developing discrete value sets is to avoid the problems of solving network equations.

Explanation: The VHDL simulator is capable of displaying the output signal waveforms which results from the stimuli or trigger applied to the input.

Explanation: The systems contain electrical signals of different strengths and it needs to compute the strength and the logic level resulting from a connection of two or more sources of electrical signals. The strength is the abstraction of the signal impedance.

Explanation: Most of the systems contain electrical signals of different strengths and levels. The level of the signal is the abstraction of the signal voltage and the strength is the abstraction of the signal impedance.