Understanding the Bus Timing Diagram of 8086 Microprocessor Video Lecture - Computer Science Engineering (CSE)

hello and welcome back in our last video
we discussed the architecture of the
eight zero eight six and its various
modes of operation today
I'm going to be talking about a bus
timing diagram and how to interpret the
bus timing diagram for eight zero eight
six
before we begin understanding what bus
timing diagrams are we must understand
the various parts of a waveform what you
see on the screen is a typical waveform
a waveform of course has a period and an
amplitude this all of us remember but a
waveform also has what's called a top
edge a bottom edge a rising edge and a
falling edge in addition the strict
definition of amplitude is when the time
was time taken to go from zero to 80%
called the rise time and the fall time
is the time taken to go from a high to
80% of high that's about 20% of low so
you got a rise time and the fall time
all of which together define a waveform
so let's look at how to read a generic
waveform so this is an example of a
clock signal a clock signal in this case
shows a transition of low to high when
the clock signal is at high so our
signal is transitioning from low to high
when the clock signal is high in this
example the signal is transitioning from
low to high when the clock signal is low
a third example is a transition from
high to low when the on the rising edge
of the clock signal so you've got
various forms of transitions that are
possible in a waveform and it's
important for you as a hardware designer
to really design it such that it meets
the requirements as mentioned by the
manufacturer in this example what
happens is that a state transition
occurs when the clock sig
hi but the transition could be from a
high to a low or a low to a high that's
the meaning of this particular signal
this is typical of address lines and
data lines where every time you could
have a high or a low on those two kinds
of buses so let's now look at a sample
bus timing diagram of the eight zero
eight six operating in the minimum mode
this is your clock signal typically for
the eight zero eight six every
instruction runs across four clock
signals t1 t2 t3 and t4 in addition you
will notice something called TW TW
stands for T weight and in certain
operations when the peripheral device is
slow it will automatically introduce a
weight state such that the processor is
forced to wait till the peripheral
device becomes ready so let's start with
understanding what's called the min
slash Matt's bar waveform the min slash
max bar tells you whether the processor
is operating at minimum mode or maximum
mode in this example the min / Max bar
transition occurs when the clock signal
is low and since it is going to stay at
high it implies that the processor is in
the minimum mode if it was operating in
the maximum mode this signal would be at
low then there is something called IO
bar / M IO is a input/output axis M
stands for memory axis in this case IO
bar tells you that this is really being
pulled high this tells you that it is a
memory operation again the straight
state transition occurs when the clock
signal is low the third control line is
something called read or write and this
is really telling you whether you are
performing a read or a write operation
and along with IO / M it tells you
whether you are performing a read or a
write operation on an i/o port or a
memory device in this case you are
reading because it is a read bar
and your reading of memory device now
the read transition occurs along with
the falling edge of the clock waveform
all three signals together are typical
control signals that you would find in
microprocessors let's now move on to the
top few address lines and in this case
that four top four address lines a 16 17
18 and 19 these address lines in the
case of the eight zero eight six are
multiplexed with this status lines s 3
to s 6 the way it works is in the first
clock pulse this set of pins carries
address information a 16 to a 19
subsequently for the remaining 3 clock
signals including weight states if any
the same pins carry the status
information and status information
you'll understand later on is used to
indicate various operational states of
the processor so these are for the top 4
address lines in addition you have of
course a 0 to a 15 and that's the bottom
set of address lines the bottom 16-bit
address lines in the case of the 8 0 8 6
this is multiplexed with the D 0 to B 15
as well the data signals as well again
the first clock signal the first clock
wave indicates a 0 to a 15 then there is
a tri-state a float condition for one
clock signal and then subsequently for
the remaining two clock signals the same
pins carry data information it acts as a
data bus how does this work when you
want to latch the address because the
address lines are going to change their
meaning so you need as a designer need
to latch the address lines at the
appropriate time and the processor is
very helpful by giving you something
called the a L ISA GLE address latch
enabled at the falling edge of the
address latch enable pin the processor
guarantees that the address bus contains
valid address information and it's your
responsibility as a
of the system to latch address
information at the falling edge of ele
then there is something called the read
bar the processor is now reading
information in this case from memory the
processor expects external devices to
guarantee information is ready on the
data bus for it to read at the rising
edge of the read bar signal it's your
responsibility as a designer to ensure
that then there is something called data
enable and the data enable is the period
in which data is guaranteed by the
processor during a write operation or it
is read back during the read operation
and external electronics devices like
memories and iOS will have to be
designed such that it matches these
requirements the last signal in this
particular set of waveforms is something
called ready I told you about the t wait
clock phase if external peripheral
device is slower than the processor
expects it to be the X it is the
responsibility of the external
peripheral device to pull the ready line
low as soon as you pull the ready line
low the processor enters a wait state
and it will continue to be in wait state
till the ready line is pulled high once
the external peripheral device is ready
it will pull the ready line high the
processes AHA it's now time for me to
read information of the data bus it then
enables the data enable signal and it
will read data from the memory device at
that point in time this in brief is an
explanation of how to read a bus timing
diagram that we spoke about the basics
of waveforms we spoke about how to read
as an example the bus timing diagram for
the eight zero eight six in minimum mode
in our next video
I am going to be talking about the
architecture of the eight zero eight six
instruction set and subsequently will
talk about specific instructions that
are more complex I hope this gave you a
feel for bus timing diagrams I
urge you to read up on of course the
minimum mode but also equally
interesting the maximum mode operations
of the eight zero eight six and try and
understand its bus timing diagrams
remember in the maximum mode you are
going to connect other processors as
well into the system till then thank you
you