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Leakage Power Dissipation - VLSI Circuits & Systems Video Lecture - Electronics and Communication Engineering (ECE)
FAQs on Leakage Power Dissipation - VLSI Circuits & Systems Video Lecture - Electronics and Communication Engineering (ECE)
| 1. What is leakage power dissipation in VLSI circuits? |  |
Ans. Leakage power dissipation refers to the power consumed by a circuit even when it is in the idle state or when there is no switching activity. It occurs as a result of the leakage currents that flow through the transistors in the circuit, even when they are supposed to be turned off. This leakage power can significantly contribute to the overall power consumption of a VLSI circuit.
| 2. How does leakage power impact VLSI circuit design? | |
Ans. Leakage power can have several negative impacts on VLSI circuit design. Firstly, it increases the overall power consumption of the circuit, which can be detrimental in terms of energy efficiency. Secondly, leakage power can lead to an increase in the temperature of the circuit, which can affect the reliability and performance of the circuit. Additionally, leakage power can also impact the battery life of portable devices, as it drains power even when the circuit is not actively being used.
| 3. What are the main sources of leakage power in VLSI circuits? | |
Ans. The main sources of leakage power in VLSI circuits are subthreshold leakage, gate oxide leakage, and junction leakage. Subthreshold leakage occurs due to the leakage current that flows through the transistor when it is in the off state but still conducts a small amount of current. Gate oxide leakage refers to the current leakage through the thin oxide layer between the gate and the channel of a transistor. Junction leakage occurs due to the reverse bias leakage current at the transistor junctions.
| 4. How can leakage power be minimized in VLSI circuits? | |
Ans. There are several techniques to minimize leakage power in VLSI circuits. One common approach is to use power gating, where certain parts of the circuit can be completely powered off when not in use. This helps to reduce leakage power significantly. Another technique is to use transistor sizing, where transistors with larger sizes are used to minimize leakage currents. Additionally, techniques such as threshold voltage scaling and voltage scaling can also be employed to reduce leakage power.
| 5. What are the trade-offs of reducing leakage power in VLSI circuits? | |
Ans. While reducing leakage power is desirable, it can come with certain trade-offs. One trade-off is increased design complexity, as implementing power gating or other leakage reduction techniques can require additional circuitry. Another trade-off is increased area overhead, as larger transistors or additional circuitry may be needed to reduce leakage power. Additionally, reducing leakage power can also lead to performance degradation, as some techniques may introduce delays in the circuit operation. Therefore, designers need to carefully consider these trade-offs while minimizing leakage power in VLSI circuits.
Text Transcript from Video
hello and welcome to today's lecture on
leakage power dissipation we are
discussing various sources of power
dissipation in CMOS circuits in the last
two lectures we have discussed the
switching power dissipation
short-circuit power dissipation and
today we shall primarily focus on
leakage power dissipation and here is
the agenda of today's lecture as I
mentioned we have discussed about
switching power dissipation
short-circuit power dissipation and as
part of the dynamic power dissipation
there is another component which is
known as glitching power so that was
left out so today I shall discuss about
this glitching power dissipation after
that we shall focus on static power
which are essentially leakage power
different types of leakage currents that
flow within the geometry of the CMOS
transistors and the this leakage power
can be broadly divided into three types
diode leakage sub-threshold leakage and
gate oxide leakage so I shall discuss
about these three types of leakage power
dissipations one after the other after
that we shall conclude our lecture
conclude this lecture after discussing
degrees of freedom okay so let us start
with glitching power dissipation earlier
I have mentioned about the the
occurrence of glitch in CMOS circuits as
I mentioned the glitch occurs in a CMOS
circuit because of finite delay of the
gates let me take up an example let us
consider a very simple circuit we have
two NAND gates let us assume here is one
NAND gate and this output is fed to
another NAND gate two input NAND gate
here you are applying a and B as input
and another input C is applied to the
third gate
okay now suppose the initially the value
of a B and C is say 0 1 and 0 that is
being applied and so what will be the
output at output 1 and output 2 since as
you know in case of a NAND gate if any
of the inputs is 0 output will be 1 so
this output is 1 and so this will be 1
and since this input is also 0 one of
the inputs is 0 output will be 1 now as
it changes from 0 1 0 to let us assume
it is changing from 0 1 0 to 1 1 1 then
what will happen if it changes from 0 1
0 to 1 1 1 then you can see these two
inputs are 1 1 so output will switch to
0 and this input is however 1 but since
one of the input is 0 output is supposed
to be 1 so we find that for both the
inputs 0 1 0 and 1 1 1 for both the
inputs output at q2 is 1 but will it be
1 throughout the time let us let us take
a I mean let us consider with respect to
time how it changes suppose this is the
sorry this is o 1 o 1 output is 1 and at
time T 0 your input is switching from 0
1 0 1 0 1 0 to 1 1 1 so this is time T
is equal to 0 and since the signal will
reach after every period of time that
means this will switch to 0 after some
time not immediately that means let us
assume this is the time the the gate
will require to switch from 1 to 0 so
this is your delta delta T or Delta
whatever you write so it will switch to
0
then of course it will remain zero that
means here the input is zero one zero
and here the input is 1 1 1 and it has
changed from 0 1 0 to 1 1 1 now what
will be the output at o2 at o2 as you
can see this input is switching to 1 to
0 after some time delta T and here what
will happen at this output so initially
it was 1 it will remain 1 up to this
period but after a after a gate delay of
Delta I mean another Delta it will
become 0 for a very brief duration that
is again Delta and then it will become 1
why this is becoming lower this is
becoming low because for this in the
during this period delta T you can see 1
in both the inputs are 1 1 this input is
1 and this input is 1 because of the
delay of this gate as a consequence both
the inputs are 1 1 after a delay time of
this gate it will be low for a 4 for the
Delta amount of time that means out is
output is becoming 0 for a brief
duration and this is typically known as
glitch and this kind of glitch very
frequently occurs in CMOS circuits
because of the finite delay of the gates
now as you know whenever the the output
switches from 0 to 1 or 1 to 0 there is
some power dissipation obviously there
will be some load capacitance at the
output and this capacitor will charge
and discharge and this will lead to what
is known as glitching power dissipation
so this glitching power dissipation will
is occurring because of finite delay of
the guest gates and you know momentarily
the outputs are switching to in this
case in this particular case we have
seen it is switching to 0 for every
brief duration and at some point it may
switch to one foregrip duration and
these are known as glitches and this
will lead to some power dissipation
known as glitching power dissipation
question arises how do you really reduce
the glitching power dissipation how can
it be reduced
is there any way by which this glitching
power dissipation can be minimized or
reduced let us have a look at this
particular example so in this case what
you have to do you have to realize
realize a and function of a B C and D so
here at the output F is equal to a dot B
dot C dot D so it is the end of four
variables a B C and D so what has been
done three and gates two input NAND
gates has been have been cascaded to
realize the function f now in this
particular case obviously there will be
some glitch at the output of q2 o2 as as
well as at the output of o3 as I have
already explained how there can be some
glitch at this output and then because
of the delay of this gate again because
of the delay of this gate there will be
some glitch at this point that means at
oh three and OH two there will be
glitches and that will lead to power
dissipation and this is typically known
as cascaded form of realization of
boolean functions now instead of that we
may realize the same function using what
is known as balanced terrorise ation so
you can see here a and B are applied to
one and gate and C and D are applied to
another and gate and then these two
outputs are applied to a third and gate
so in this particular case we notice
that the output is actually same for
both the cases number of gates is
remaining same for both the cases but
what we have achieved is I mean
reduction in glitching participation why
the reason for that is you can see at
this point the signal will reach at the
same time at this point so there is no
delay I am a difference in delay between
the two signals that will be reaching
here and as a consequence the clear the
because of this balance realization the
glitching power dissipation is reduced
and of course another secondary
advantage of this that that critical
path delay also will be lower in this
particular case compared to this because
here the critical path is through 3 and
gates here the critical path is to the
two and gates
so apart from reducing the critical path
delay it is reducing the witching power
dissipation so we may conclude by saying
that we can reduce the glitching power
dissipation by realizing circuits in a
balanced form so instead of cascaded
form we shall try to realize in in the
balanced form that we will realize the
will you reduce the glitching power
dissipation so with this we have come to
the end of our discussion on dynamic
power dissipation now we shall focus on
leakage power dissipation and first we
shall discuss about the different
components of leakage power I have
already told that the the leakage
essentially can be divided into three
types of leakage gate leakage and again
yeah that the diode leakage gate leakage
and the leakage through the channel so
there is a sub threshold leakage you can
say there will be three different types
of leakage currents now here we have
drawn a transistor a it can be in it may
be NMOS or PMO's and does not really
matter a MOS transistor it may be N Mo's
or P Mo's does not matter and and here
are the different leakage currents that
flow in a MOS transistor and
particularly
taken this from this paper by coffee
grower his group published in
Proceedings of IEEE Tripoli back in
February 2003 so the discussion on this
conference of leakage power is taken
from this particular paper so here we
find there are seven different snick
edge currents that are flowing in this
transistor so first to reverse pass PN
Junction diode leakage current and
band-to-band tunnelling current these
two are essentially diode leakage
currents i1 and i2 are diode leakage
currents i1 and i2 and i3
which is passing through the the channel
which is essentially sub-threshold
leakage current which I mentioned
earlier and then there are gate leakage
currents I 4 and i-5 these two are gate
leakage currents gate oxide tunneling
current and gate current due to hot
carrier injection so these two are gate
leakage currents in addition to that
there are two more leakage currents
which is known as channel punch-through
so that is this is i6 channel punch
through which will flow between the
source and drain and force last one is
gate induced drain leakage current that
passes through from the you know to the
goes to the substrate so through the
from the channel so here these are the
different currents but the first five
are more most dominant and channel punch
through occasionally occurs I mean if it
if the design is not proper and gate
induced drain leakage current of course
is present here and I shall discuss
about these leakage currents one after
the other first let us focus on reverse
bias leakage current where from this
reverse bias leakage current occurs here
we have got a see most CMOS inverter
shown here so here you can see this is
the N Mo's transistor and here is the P
Mo's transistors realized in if n well
so in in an N well the P Mo's transistor
has been realized and the
you on the feeder pbut we type substrate
there is a NMOS transistor so you have P
Mo's transistor and n MOS transistor and
you can see the input the this is one
gate this is another gate where we have
applied a voltage VDD to the gate inputs
and this is the output so gates are
input and this is the output the the
source and drain of the fema n Mo's and
P Mo's transistors are tied together to
get the output now we can see within the
geometry of the device we have got a
junction diodes this is a p+ type region
heavily doped P plus region and this is
n well so you have got p-n-p-n diode
junction diode is here here also P plus
region and this is n well so there is a
diode here similarly hey this is the n
plus region which is the drain of the N
Mo's transistor and this is a p-type
substrate so you have got NP diode and
here also there is another diode so NP
diode so I can draw the diodes as you
can see all the diodes are do not shown
here so this is the within the geometry
of the device there are some junction
diodes which are present because of the
the way the MOS transistors are realized
and then during normal mode of operation
these diodes are reverse biased that is
why it is called reverse bias leakage
current as you know when a diode is
reverse biased some current will flow
and that reverse bias current if I call
it leakage current but usually it is
known as the reverse bias diode current
junction diode current and that is
essentially a leakage current in this
particular context of MOS transistors
and the expression for PN Junction
reverse bias leakage current is shown
here ID is equal to is into e to the
power minus QV by KT minus 1 where is is
the reverse saturation current density V
is the diode voltage volt
applied across the diode q is the charge
of the electron K is the Boltzmann
constant and T is the temperature in
Kelvin absolute temperature so you can
see Q by K T QV by K T and like that so
the current is in the range of 0.1 nano
ampere 2.5 nano ampere you see this the
the amount of current will be dependent
on the size of the junction the junction
area so Junction area is is dependent is
actually the dependent on the junction
area and that is why as the size is
reducing this current will obviously
reduce but the number of transistors
will increase and because of this factor
you know that temperature the current
doubles for every 10 degree increase in
temperature so this is a temperature
dependent current now although this
current is quite small for a single
diode the since you have got millions of
transistors in a single most circuit
nowadays you have got say 100 million
transistors and a single most circuit
and obviously total sum total of the
leakage current due to reverse bias Li
reverse biased diodes cannot be very
small here some example is given say
total static power dissipation due to
diode leakage current of 1 million
transistors is given by P is equal to
VDD into summation of this I di that is
1 to 10 to power 6 1 million so that
comes to be point 0 1 micro watt so
point 0 1 micro watt may appear to be
small but whenever we are realizing
circuits for embedded applications which
will be used as sense in sensor network
where the life of the system depends on
the life of the battery in such
situations even micro ampere of current
is not small it has to be much lower so
it cannot be neglected when we are
considering that type of applications
however as we shall see this component
is low as smaller than other components
for example there are two types of die
currents this is one another one is
known as band-to-band tunnelling current
in fact in deep submicron technologies
this band-to-band tunnelling current is
becoming higher than the reverse bias
diode leakage current what is
band-to-band tunnelling current you know
those diodes we have as we have told
those are reverse biased and because of
the first biased diodes a voltage is
developed across those diodes and high
electric field is across this reverse
bias PN Junction diodes causes
significant current known as
band-to-band tunnelling current why you
are calling is band-to-band tunnelling
current here as you can see electrons
are moving from the substrate to the to
the to the gate that is your poly
silicon when to benton and now so here
diode is from the substrate to the
source or drain not not really the gate
so here we have seen here diode is there
so across this so from the substrate to
the source or drain I mean depending on
whatever use is your so what is
happening because of the voltage drop
you can see the electrical barrier is
lowered and as a result the electrons
will move from the valence band to the
conduction band and as a result this way
there will be a flow of current so it
because of this it is the electrons are
moving from one band to another band
equivalency band 2 electron band on the
other side of the junction this is this
will lead to a flow of current and so
you can see the band gap is overcome
because of the electric field that is
being applied and this electrons will
move because of the positive voltage
applied on the drain and as a
consequence this current is become is is
not very small as the GMA
is gradually reduced as the geometry is
gradually reduced that electric field
become the across the diode cannot can
be substantial and it has been found
that this this current is dominating the
PN Junction leakage current that means
in deep submicron sub micron technology
that bt bt current band-to-band
tunnelling current is larger than the
leakage current so a lot of attention is
is focused on the for the reduction of
this band-to-band tunnelling current
okay so this is the main tube and
tunneling current now let us move on to
the I mean let us consider the equation
let us not go into the details of this
equation this is essentially say complex
equation derived from from the knowledge
of semiconductor device physics but from
this expression you can find out its
dependence on various parameters
obviously it has defined it as
dependence on the voltage it has
dependence on the mobility of the device
mass mass of the electron or hole and
charge and this is H is Planck's
constant so that means this current is
predominant I mean only for holes not
for I mean electrons not for homes so in
case of deep submicron technology high
doping concentration and abrupt doping
profiles are responsible for significant
bt bt current actually as you know
whenever we are going from one
technology to another technology the
dimensions are reduced later on I shall
discuss about it in more detail and but
to maintain constant field usually the
supply voltage is also reduced but to
maintain the electric field you have to
increase the doping concentration so
doping concentration is in is being
increased gradually and also the doping
profile is not very smooth abrupt
lowering profile because of
fabrication of a smaller dimension
devices and this is responsible for
significant band-to-band tunnelling
current went to banned tunneling current
okay so this is in brief discussion
about the band-to-band tunnelling
current and now let us focus on sub
threshold leakage current the sub
threshold leakage current is a very
significant component of the leakage
power and this current passes from drain
to source through the channel normally
we know that you know normally we assume
that for for vgs less than VT ids is
equal to zero that means there is no
channel if the gate voltage is less than
the threshold voltage and on drain
current will start flowing only when the
gate voltage is larger than the
threshold voltage of the device but in
practice that is not true particularly
when the gate voltage is increased from
zero and it becomes closer to the
threshold voltage there is significant
amount of channel current that flows and
that is known as sub threshold leakage
current because since it is occurring
for a gate voltage less than the
threshold voltage that is why the name
sub threshold leakage current so the sub
threshold leakage current is a
significant component of the leakage
current a current that flows between the
source and drain and here is the
expression for the sub threshold leakage
current a is a kind of constant
primarily depends on the fabrication
length width and various other
parameters then QB Q by n SKT and VG is
the gate voltage v s is a substrate
voltage and V t0 is essentially the
threshold voltage with zero body bias
zero bias of the zero biasing on the
substrate and this delta - vs is is the
is due to the to take into account the
body bias effect later on you will see I
shall mention about this body effect
when the substrate is not connected to
the source
if a voltage is applied it can be
positive body bias or it can be reverse
negative body bias whatever whenever the
body bias is really negative then you
will see that threshold voltage is
increased when it is positive the
threshold voltage will be will be
reduced and as a consequence it has
impact on the leakage current I have
already mentioned about this so this is
this Delta - is essentially the sub
threshold 2k 2k to take into account
body effect so this is known as body
bias coefficient and this this
particular parameter this is this this
particular parameter is to take into
account the effect of double effect then
- then - you know whenever you apply a
drain voltage double effect then drain
induced barrier lowering so so take into
account body effect and develop X this
is the expression for sub threshold
leakage current and as you can see here
also there is a dependence on the
temperature Q by K T and this current
increases drastically with temperature
and it is also increases at threshold
voltage is scaled as you know whenever
threshold voltage is reduced you know
this this particular current will
increase and whenever we do device size
scaling then threshold voltage is also
scaled that means you know let us
consider the situation suppose you are
reducing the dimension by a factor of K
then as you reduce the dimension by a
factor ik by K usually the supply
voltage is also reduced
by a factor of K VDD is begin a new VDD
is K P DD similarly the threshold
voltage is also reduced at the same
proportion sir kV T so it is also raise
a factor a reduction factor so as you do
that that means supply voltage is
reduced to keep the field constant and
as you do that to maintain performance
or you have to reduce the threshold
voltage but as you do that the leakage
current increases that means this this
this reduction in threshold voltage
leads to increase in leakage current
that is that is the reason why as the
device dimensions are reduced as you go
from one technology generation to the
new technology generation leakage
current increases because of the
reduction in the threshold voltage so
this this has to be taken into
consideration how we can really reduce
this sub threshold leakage current this
is a very important area
I mean point of concern and people lot
of people are concentrating on how the
this current can be reduced and in fact
one important direction is to use high K
dielectric so that the thickness of the
silicon dioxide layer is is larger so
using high K dielectric the maybe this
layer the leakage current can be reduced
to some extent but again this is another
I mean the one way of reducing the sub
threshold leakage current and the sub
threshold leakage current has dependence
on a number of parameters vary there are
various mechanism which continues
contributes to the sub threshold leakage
current one is your I have already
mentioned drain induced barrier lowering
nibble effect second is body effect
third is narrow width effect forties
effect of channel length on and Vth
roll-off and there is a impact of
temperature effect of temperature so let
us very briefly consider how the
threshold sub threshold leakage current
is affected because of these effects
first of all drain induced barrier
lowering in this particular diagram as
you can see I have plotted the lateral
energy band diagram at the surface
versus the distance so you can see here
this side is the source and the size is
a drain so here this is the Y by L
length is the channel length and so as
the length is I mean the on this side we
are going it is closer to the drain and
this side it is closer to the source and
the energy band diagram is shown now it
is not drawn for three different
parameters by varying the length L and
second one is by varying the drain drain
voltage VDS so first one is you can see
the length of the channel is long six
point two five micron and the gate with
the end voltage is also small point five
volt so in that case you can see curve
is more or less perfect I mean the
energy that energy band diagram is what
is what it should be and as a
consequence the the threshold voltage a
will be I mean you have to apply the
gate voltage higher than the threshold
voltage so that to induce channel
current and so on in other words the
threshold voltage is high and leakage
current will not be high on the other
hand as you can see in case of car B and
curve C curve B corresponds to 1.25
micron length is small and supply
voltage is small also and last one
the length is small supply voltage is
large that means whenever you have got
small dimension and large supply voltage
then you can see there is a significant
lowering of the bed
of the energy band diagram whenever
there is a lowering of the energy band
diagram what what happens you require
lower voltage to induce current and that
leads to reduction in threshold voltage
and as the threshold voltage is reduced
what happens the leakage current sub
threshold leakage current increases so
so we find that this is essentially
effect which is due to read of smaller
dimension of the channel or a lot
normally we call it short channel effect
this is one of the short channel effects
and it becomes predominant when the
drain voltage is large as it is evident
from this diagram okay so this is the or
drain induced barrier lowering and I
have already shown you the expression
for the drain current of the of that X
you know that this expression the sub
threshold leakage current where the that
VDS has been taken into consideration
the impact of daredevil attending this
very alluring second is the body effect
I have already mentioned about this
while discussing the threshold voltage
there we have seen that you know instead
of connecting the substrate to source
for example this is a n MOS type
transistor this is n plus n plus this is
the channel region here you have got the
gate this is the gate now here you have
got a P plus region which is normally
connected to source then it is grounded
so here this is a substrate is down dead
connected to source and then grounded so
in this case there is a zero body bias
now suppose you apply a negative voltage
to it with respect to source so then we
are calling it a reverse body bias
so you can apply a different substrate
bias voltage with respect to the source
and that we will actually change the
threshold voltage how it why it changes
I mean the expression is there but
physically what what occurs what is the
physical phenomenon actually as the
negative voltage is applied to the
substrate with respect to the source the
way to source Junction well to source
Junction the device is reverse biased
and both depletion region is widened so
the depletion region bulk depletion
region is widened that means this region
is there is a depletion region you know
this depletion region is widened so
whenever it is widened it becomes wider
obviously you will require a larger
voltage to be applied to the gate to
induce to induce a channel that means
the to overcome the depletion region and
to create to to form the you know that
inverse to create the inversion layer a
larger voltage is required in other
words threshold voltage is increased so
this is the that is the reason why
whenever reverse body bias is increased
threshold voltage is increased on the
other hand you can apply a positive
requires voltage to the substrate with
respect to the source in that case there
will be reduction in the threshold
voltage and both you can do but normally
to reduce the leakage power it is
essential to increase the threshold
voltage so you have to apply reverse
body bias on the other hand if you are
interested in increasing the performance
not the
not to reduce the leakage current then
you can apply forward body bias to
uniquely reduce the threshold voltage
that will improve the performance so
that also can be done but our interest
is to reduce the leakage current so this
is the body effect so you can see in
this particular curve the how the body
effect is changing the drain current so
here there is a plot off on the x-axis
you have got the gate voltage on the
y-axis you have the drain current in
logarithmic form so it is a kind of log
linear curve so y-axis log logarithmic
and Y x-axis linear that is that voltage
is linear now you can see when the zero
gate voltage is there even then there is
a current flow so there is a drain
current and that drain current when the
gate voltage is zero that means the
substrate is connected to the substrate
is connected to the source then you can
see this is the current whenever you in
P input increase the reverse body bias
is the the substrate is connected to
minus 1 minus 2 minus 3 minus 4 and
minus 5 you can see these are the
different curves and the lower tab
corresponds to a reverse body bias of
minus 5 volt so you can see for zero
gate voltage for different body bias how
the current is reducing so this current
is you can see what is the order of
magnitude difference roughly for order
of magnitude difference in leakage
current this is 1 into 10 to the power
minus 12 ampere and this is 1 into 10 to
the power minus 8 ampere so you can see
for order of magnitude of reduction in
leakage current is possible by reverse
body biasing so this particular curve
the shows the impact of body effect
on the leakage current sub threshold
leakage current coming to the narrow
with effect you know we have discussed
about the effect of the length now we
are considering the effect of the width
when the width is small that too has an
impact on the threshold voltage so here
we see how the gate with affects the
threshold voltage you can see when the
width is large of the order of say 2 to
10 micron you can see it has no impact
on the threshold voltage that means
threshold voltage is more or less
independent of the width so it does not
change but whenever it is small less
than 1 micron
less than a micron you can see
particularly when the when the gate
voltage is large the body bias is body
bias particularly when the body bias is
large there you can see there is a
lowering of the threshold voltage and
this lowering of the threshold voltage
occurs whenever the width is small less
than a less than 1 micron and you can
see the threshold voltage decreases
sharply so because of this narrow width
effect the threshold voltage is reduced
and that leads to increase in the sub
threshold leakage current and let us
consider the Vth role of you know
normally the gate voltage the you're
applying supply some voltage to the gate
also you are applying voltage to the
drain as you know to attract the
electrons from the source or you apply
positive voltage to the drain that is
how the current flows now let us have a
look at the channel region channel
region is shown here it you can see the
length is L from here to here
from if you consider from this point to
this point this is the lane but whenever
you apply a positive drain voltage
it creates depletion regions like this
these are the depletion regions because
of these depletion regions it is no
longer I mean if the channel and channel
length is no longer L in the lower part
of the channel so you can see it is no
longer a kind of rectangle but it takes
the shape of a trapezoidal and as a
consequence the effective area reduces
effective volume you can say volume of
the channel reduces so whenever the
volume of the channel reduces what
impact it has got now it has got the
impact of lowering of the threshold
voltage that means the area at the
volume is reduced that means he will
require smaller voltage to create
inversion layer in the channel and if
the volume is large then you will leak a
larger volume voltage to create the
inversion voltage in the channel and and
as a consequence what happens when the
channel when the channel when the
channel you can see when the channel
length is reduced you can see
particularly this is also a short
channel effect there is a kind of roll
off of the threshold voltage and this is
typically known as VT h0 log that means
ETH role of occurs when the channel
length is small and particularly device
dimensions are less than the very close
to the submicron region and as a
consequence the leakage current sub
threshold leakage current increases this
is the VT h role of coming to the
temperature effect we have and we have
shown you I have shown you the plot of
the drain current with respect to the
gate voltage and we have seen there is a
slope that slope is significantly effect
by the temperature and and this is known
as sub threshold slope so there is there
is strong dependence of threshold
voltage on temperature particularly the
sub threshold slope is affected sub
threshold slope St is represented by 2.3
into KT by Q into 1 plus C DM by C do X
these are essentially some capacitances
within the geometry let us not bother
about that
those are dependent on the physical
fabrication parameters but here you can
see the temperature is here and there is
linear dependence of sub session subsys
on slope on the temperature and actually
this plot will illustrate it as you can
see here I have drawn the same diagram
shown same plot is shown but for
different temperature here the gate
voltage has been kept fixed two point
seven volt and on this side on the
y-axis the drain current is plotted in
logarithmic plot and gate then gate
voltage in linear plot these are the
dead band voltages gate voltage s so you
can see at zero gate voltage these are
the different currents and the lower
curve corresponds to minus 50 degree
centigrade the upper curve correspond to
100 degree centigrade so you can see the
slope is changing as you are increasing
the temperature slope is changing and as
a consequence currently changing the
leakage current sub threshold leakage
current is changing here also as you go
from minus 50 degree centigrade to 100
degree centigrade you can see there is
about I think 6 order of magnitude
difference in the sub threshold leakage
current so here for minus 50 degree
centigrade for 4 point 5 into 10 into 10
to power minus 13 ampere and for 100
degree centigrade it is 7 point 6 7 into
10 to the power minus 9 ampere so you
see for order of magnitude rather 4
point 5 or 4 order of magnitude
difference in the sub threshold leakage
current that is occurring
so this is the temperature effect so we
have discussed about the various effects
there are on the sub threshold leakage
current now let us focus on the those
get you know kind of current through the
gate oxide tunneling through gate oxide
now why why do tunnelling occurs through
gate oxide the tunneling through gate
oxide is occurring because the thickness
of the gate oxide layer is gradually
reduced as you go from one technology
generation to another technology
generation length is reduced width is
reduced the thickness of the silicon
dioxide is also reduced in the present
day technology will be surprised to know
that sickness of the silicon dioxide
layer is nothing but few layers of
molecules and as a consequence what
happens you whenever you apply a gate
voltage that leads to tunneling of
current this is illustrated with the
help of this three diagrams here you can
see this is the flat band condition
where no voltage is applied to the gate
now
as you apply apply positive voltage to
the gate you can see this is the P
substrate and this side is the gate as
you apply a positive voltage the the
energy band diagram is lowered because
of this voltage applied to the gate and
you can see electrons is passing from
the substrate through the gate oxide
layer to the gate so tunneling of
electrons is occurring through the
silicon dioxide layer normally we assume
that silicon dioxide is a pure insulator
no current can flow through it but this
is not happening in deep submicron
technology because of this tunneling
through gate oxide and not only
electrons the holes can also pass
through the gate whenever you apply a
negative voltage to the gate but because
of higher mobility of holes
it is unlikely that the the holes will
pass through the gate XM in through the
gate oxide that means whenever you apply
a negative gate bias there is a
possibility that holes will also tunnel
through the silicon dioxide layer but
that usually does not happen primarily
because we normally apply a positive
gate voltage and because of lower
mobility of electrons they they tunnel
through the silicon dioxide layer so
tunneling of electrons to the N Mo's
capacitor with a heavily doped n plus
polysilicon gate and p-type substrate
that is shown in this diagram now there
is another you know gate gate leakage
that is known as hot carrier injection
you know whenever you are applying a
gate voltage may be whatever may be very
small but because of the smaller
thickness of the silicon dioxide layer
that electric field is so high that it
creates some electrons of very heavy
very high energy that means electrons
acquire very high energy those are known
as hot electrons those hot electrons
acquire so much energy they can pass
through this silicon dioxide layer now
that is what is happening in this
particular key case you can see the
electrons are passing passing through
the because of the high electric field
passing through the silicon dioxide
layer going from the substrate to the
polysilicon of the gate region so
injection of hot electrons from the
substrate to oxide due to high electric
field near silicon-silicon dioxide
interface because of smaller geometry of
the silicon dioxide so this is known as
hot carrier injection so these are the
two phenomenon responsible for gate
leakage one is your hot carrier
injection and another is your gate gate
induced drain leakage sorry another is
your tunnelling through gate oxide
coming to the another phenomenon that is
your g ideal gate induced drain leakage
now you know this happens because of due
to high electric field in that drain
Junction
you can see there is an overlap of great
gate and drain and here there is a high
electric field that leads to you know
those electrons you can see these
electrons are moving from this region
and going to the substrate and that
leads to current what is known as gate
induced drain your drain leakage and
this is due to a high electric field in
that drain Junction so these are all
arising out of a short length and high
electric field created because of
smaller dimension and even a small valid
a voltage can create large electric
field coming to the last phenomenon that
is punched through the punch through
voltage PPT okay let me briefly explain
what do you really mean by punch through
so this is the most transistor again I
am drawing say this is your say source n
plus n plus source so this is source
this is drain now whenever the and this
is the gate region here you have got
poly silicon layer Scylla silicon on top
of silicon dioxide now whenever you
apply a positive voltage there is a
there is a you know this is the
depletion region now as you increase the
drain voltage what happens these these
depletion regions widens and it may so
happen that depletion regions will touch
each other
this is known this this is known as
punch-through when the two depletion
regions touch each other and that point
we known as punch-through has occurred
and this points through voltage VP T
before the gate drain voltage when it
occurs estimates the value of the VD s
for which punch through occurs at vgs is
equal to 0 that means obviously this
punch through voltage is dependent on
the gate voltage as well when the gate
voltage is small
and finally this is defined as the punch
through voltage fan gate voltage is zero
and this is represented by this
expression v PT into alpha n B into L
minus WJ cubed so NB is the doping
concentration of the bulk l is the
length of the channel WJ is the junction
weight so points through increases sub
threshold current and degrades the sub
threshold slope so this is the impact of
the punch through and in this particular
diagram different types of leakage
currents that I have drawn explained are
shown a summary of that is shown here
for example this is the zero gate
voltage where there is a quadrant
current because of weak inversion that
is sub threshold leakage current and
Junction leakage current and then
because of the IBL effect then induce
barrier lowering and gate induce del
leakage current you can see there are
more currents
I mean currents are increasing so you
see so n channel current drain current
versus gate voltage lust rating various
leakage currents components are shown in
this particular diagram for different
drain voltages is the Sun and so you can
see that we can we can tell that this
leakage current is is very there is very
important and there are different
components and these components I have
explained in detail now let me conclude
with another very important point
particularly the leakage current you can
see the we have two two lines the top
one is drain current the bottom one is
leakage current or standby current you
can see the slope of this is larger than
the upper one that means the leakage
current is increasing at a faster rate
than the than the active current active
current or you can say dynamic current
now leakage current will be
significantly higher that will be more
clear from this particular diagram you
can see here for 0.25 micron technology
indicate leakage current is
insignificant but for 0.18 micro micron
it is visible it is significant
component of the active current but
whenever we go to point zero seven
micron that is your 70 nanometer you can
see the leakage current component is
more than the dynamic current component
that means leakage current leakage power
is becoming a large component of the
total power dissipation what is the
impact of that impact of that is you
have to reduce runtime leakage current
what you really mean by that earlier
people were developing techniques by
which you can reduce the dynamic power
when the circuit is in operation circuit
is active and leakage current was
reduced when the circuit was in standby
mode but now since the leakage current
component is a significant component of
the dynamic power when the circuit is
active it is in runtime condition then
also you have to reduce the leakage
current that means runtime leakage power
reduction is becoming a very important
research area in the present context
okay with this let me discuss about the
various degrees of freedom I have
discussed about different types of power
dissipation switching power dissipation
short-circuit power dissipation leakage
power dissipation we find from this
expression different parameters are
present which parameters are important
rather how can you really reduce this
power the power dissipation the first
and the most important one is the supply
voltage we find that supply voltage is
present in quadratic from in cubic form
or
linear form so in all these expression
supply voltage is common everywhere it
is present and that is the reason why
read supply voltage reduction is the one
of the most important technique that is
being used to reduce power dissipation
then of course physical capacitance CL
CI that has to be reduced then switching
activity alpha L alpha I reduction of
physical capacitance and reduction of
switching activity these two are to be
reduced to reduce the dynamic power then
threshold voltage reduction is necessary
particularly to reduce the leakage power
dissipation we have seen that leakage
power is has exponential dependence on
the threshold voltage so based on this
discussion I shall be discussing various
techniques of power reduction of I mean
fellow and I mean know for techniques
and they can be broadly divided into
three categories first was first one is
supply voltage scaling second one is
minimizing switched capacitance they are
essentially we shall be minimizing
capacitance value as well as the
switching activity and last one is
minimizing leakage power primarily by
controlling the threshold voltage so
from next class onwards we shall
concentrate on various techniques for
reducing power dissipation rather low
power techniques thank you
you
leakage power dissipation we are
discussing various sources of power
dissipation in CMOS circuits in the last
two lectures we have discussed the
switching power dissipation
short-circuit power dissipation and
today we shall primarily focus on
leakage power dissipation and here is
the agenda of today's lecture as I
mentioned we have discussed about
switching power dissipation
short-circuit power dissipation and as
part of the dynamic power dissipation
there is another component which is
known as glitching power so that was
left out so today I shall discuss about
this glitching power dissipation after
that we shall focus on static power
which are essentially leakage power
different types of leakage currents that
flow within the geometry of the CMOS
transistors and the this leakage power
can be broadly divided into three types
diode leakage sub-threshold leakage and
gate oxide leakage so I shall discuss
about these three types of leakage power
dissipations one after the other after
that we shall conclude our lecture
conclude this lecture after discussing
degrees of freedom okay so let us start
with glitching power dissipation earlier
I have mentioned about the the
occurrence of glitch in CMOS circuits as
I mentioned the glitch occurs in a CMOS
circuit because of finite delay of the
gates let me take up an example let us
consider a very simple circuit we have
two NAND gates let us assume here is one
NAND gate and this output is fed to
another NAND gate two input NAND gate
here you are applying a and B as input
and another input C is applied to the
third gate
okay now suppose the initially the value
of a B and C is say 0 1 and 0 that is
being applied and so what will be the
output at output 1 and output 2 since as
you know in case of a NAND gate if any
of the inputs is 0 output will be 1 so
this output is 1 and so this will be 1
and since this input is also 0 one of
the inputs is 0 output will be 1 now as
it changes from 0 1 0 to let us assume
it is changing from 0 1 0 to 1 1 1 then
what will happen if it changes from 0 1
0 to 1 1 1 then you can see these two
inputs are 1 1 so output will switch to
0 and this input is however 1 but since
one of the input is 0 output is supposed
to be 1 so we find that for both the
inputs 0 1 0 and 1 1 1 for both the
inputs output at q2 is 1 but will it be
1 throughout the time let us let us take
a I mean let us consider with respect to
time how it changes suppose this is the
sorry this is o 1 o 1 output is 1 and at
time T 0 your input is switching from 0
1 0 1 0 1 0 to 1 1 1 so this is time T
is equal to 0 and since the signal will
reach after every period of time that
means this will switch to 0 after some
time not immediately that means let us
assume this is the time the the gate
will require to switch from 1 to 0 so
this is your delta delta T or Delta
whatever you write so it will switch to
0
then of course it will remain zero that
means here the input is zero one zero
and here the input is 1 1 1 and it has
changed from 0 1 0 to 1 1 1 now what
will be the output at o2 at o2 as you
can see this input is switching to 1 to
0 after some time delta T and here what
will happen at this output so initially
it was 1 it will remain 1 up to this
period but after a after a gate delay of
Delta I mean another Delta it will
become 0 for a very brief duration that
is again Delta and then it will become 1
why this is becoming lower this is
becoming low because for this in the
during this period delta T you can see 1
in both the inputs are 1 1 this input is
1 and this input is 1 because of the
delay of this gate as a consequence both
the inputs are 1 1 after a delay time of
this gate it will be low for a 4 for the
Delta amount of time that means out is
output is becoming 0 for a brief
duration and this is typically known as
glitch and this kind of glitch very
frequently occurs in CMOS circuits
because of the finite delay of the gates
now as you know whenever the the output
switches from 0 to 1 or 1 to 0 there is
some power dissipation obviously there
will be some load capacitance at the
output and this capacitor will charge
and discharge and this will lead to what
is known as glitching power dissipation
so this glitching power dissipation will
is occurring because of finite delay of
the guest gates and you know momentarily
the outputs are switching to in this
case in this particular case we have
seen it is switching to 0 for every
brief duration and at some point it may
switch to one foregrip duration and
these are known as glitches and this
will lead to some power dissipation
known as glitching power dissipation
question arises how do you really reduce
the glitching power dissipation how can
it be reduced
is there any way by which this glitching
power dissipation can be minimized or
reduced let us have a look at this
particular example so in this case what
you have to do you have to realize
realize a and function of a B C and D so
here at the output F is equal to a dot B
dot C dot D so it is the end of four
variables a B C and D so what has been
done three and gates two input NAND
gates has been have been cascaded to
realize the function f now in this
particular case obviously there will be
some glitch at the output of q2 o2 as as
well as at the output of o3 as I have
already explained how there can be some
glitch at this output and then because
of the delay of this gate again because
of the delay of this gate there will be
some glitch at this point that means at
oh three and OH two there will be
glitches and that will lead to power
dissipation and this is typically known
as cascaded form of realization of
boolean functions now instead of that we
may realize the same function using what
is known as balanced terrorise ation so
you can see here a and B are applied to
one and gate and C and D are applied to
another and gate and then these two
outputs are applied to a third and gate
so in this particular case we notice
that the output is actually same for
both the cases number of gates is
remaining same for both the cases but
what we have achieved is I mean
reduction in glitching participation why
the reason for that is you can see at
this point the signal will reach at the
same time at this point so there is no
delay I am a difference in delay between
the two signals that will be reaching
here and as a consequence the clear the
because of this balance realization the
glitching power dissipation is reduced
and of course another secondary
advantage of this that that critical
path delay also will be lower in this
particular case compared to this because
here the critical path is through 3 and
gates here the critical path is to the
two and gates
so apart from reducing the critical path
delay it is reducing the witching power
dissipation so we may conclude by saying
that we can reduce the glitching power
dissipation by realizing circuits in a
balanced form so instead of cascaded
form we shall try to realize in in the
balanced form that we will realize the
will you reduce the glitching power
dissipation so with this we have come to
the end of our discussion on dynamic
power dissipation now we shall focus on
leakage power dissipation and first we
shall discuss about the different
components of leakage power I have
already told that the the leakage
essentially can be divided into three
types of leakage gate leakage and again
yeah that the diode leakage gate leakage
and the leakage through the channel so
there is a sub threshold leakage you can
say there will be three different types
of leakage currents now here we have
drawn a transistor a it can be in it may
be NMOS or PMO's and does not really
matter a MOS transistor it may be N Mo's
or P Mo's does not matter and and here
are the different leakage currents that
flow in a MOS transistor and
particularly
taken this from this paper by coffee
grower his group published in
Proceedings of IEEE Tripoli back in
February 2003 so the discussion on this
conference of leakage power is taken
from this particular paper so here we
find there are seven different snick
edge currents that are flowing in this
transistor so first to reverse pass PN
Junction diode leakage current and
band-to-band tunnelling current these
two are essentially diode leakage
currents i1 and i2 are diode leakage
currents i1 and i2 and i3
which is passing through the the channel
which is essentially sub-threshold
leakage current which I mentioned
earlier and then there are gate leakage
currents I 4 and i-5 these two are gate
leakage currents gate oxide tunneling
current and gate current due to hot
carrier injection so these two are gate
leakage currents in addition to that
there are two more leakage currents
which is known as channel punch-through
so that is this is i6 channel punch
through which will flow between the
source and drain and force last one is
gate induced drain leakage current that
passes through from the you know to the
goes to the substrate so through the
from the channel so here these are the
different currents but the first five
are more most dominant and channel punch
through occasionally occurs I mean if it
if the design is not proper and gate
induced drain leakage current of course
is present here and I shall discuss
about these leakage currents one after
the other first let us focus on reverse
bias leakage current where from this
reverse bias leakage current occurs here
we have got a see most CMOS inverter
shown here so here you can see this is
the N Mo's transistor and here is the P
Mo's transistors realized in if n well
so in in an N well the P Mo's transistor
has been realized and the
you on the feeder pbut we type substrate
there is a NMOS transistor so you have P
Mo's transistor and n MOS transistor and
you can see the input the this is one
gate this is another gate where we have
applied a voltage VDD to the gate inputs
and this is the output so gates are
input and this is the output the the
source and drain of the fema n Mo's and
P Mo's transistors are tied together to
get the output now we can see within the
geometry of the device we have got a
junction diodes this is a p+ type region
heavily doped P plus region and this is
n well so you have got p-n-p-n diode
junction diode is here here also P plus
region and this is n well so there is a
diode here similarly hey this is the n
plus region which is the drain of the N
Mo's transistor and this is a p-type
substrate so you have got NP diode and
here also there is another diode so NP
diode so I can draw the diodes as you
can see all the diodes are do not shown
here so this is the within the geometry
of the device there are some junction
diodes which are present because of the
the way the MOS transistors are realized
and then during normal mode of operation
these diodes are reverse biased that is
why it is called reverse bias leakage
current as you know when a diode is
reverse biased some current will flow
and that reverse bias current if I call
it leakage current but usually it is
known as the reverse bias diode current
junction diode current and that is
essentially a leakage current in this
particular context of MOS transistors
and the expression for PN Junction
reverse bias leakage current is shown
here ID is equal to is into e to the
power minus QV by KT minus 1 where is is
the reverse saturation current density V
is the diode voltage volt
applied across the diode q is the charge
of the electron K is the Boltzmann
constant and T is the temperature in
Kelvin absolute temperature so you can
see Q by K T QV by K T and like that so
the current is in the range of 0.1 nano
ampere 2.5 nano ampere you see this the
the amount of current will be dependent
on the size of the junction the junction
area so Junction area is is dependent is
actually the dependent on the junction
area and that is why as the size is
reducing this current will obviously
reduce but the number of transistors
will increase and because of this factor
you know that temperature the current
doubles for every 10 degree increase in
temperature so this is a temperature
dependent current now although this
current is quite small for a single
diode the since you have got millions of
transistors in a single most circuit
nowadays you have got say 100 million
transistors and a single most circuit
and obviously total sum total of the
leakage current due to reverse bias Li
reverse biased diodes cannot be very
small here some example is given say
total static power dissipation due to
diode leakage current of 1 million
transistors is given by P is equal to
VDD into summation of this I di that is
1 to 10 to power 6 1 million so that
comes to be point 0 1 micro watt so
point 0 1 micro watt may appear to be
small but whenever we are realizing
circuits for embedded applications which
will be used as sense in sensor network
where the life of the system depends on
the life of the battery in such
situations even micro ampere of current
is not small it has to be much lower so
it cannot be neglected when we are
considering that type of applications
however as we shall see this component
is low as smaller than other components
for example there are two types of die
currents this is one another one is
known as band-to-band tunnelling current
in fact in deep submicron technologies
this band-to-band tunnelling current is
becoming higher than the reverse bias
diode leakage current what is
band-to-band tunnelling current you know
those diodes we have as we have told
those are reverse biased and because of
the first biased diodes a voltage is
developed across those diodes and high
electric field is across this reverse
bias PN Junction diodes causes
significant current known as
band-to-band tunnelling current why you
are calling is band-to-band tunnelling
current here as you can see electrons
are moving from the substrate to the to
the to the gate that is your poly
silicon when to benton and now so here
diode is from the substrate to the
source or drain not not really the gate
so here we have seen here diode is there
so across this so from the substrate to
the source or drain I mean depending on
whatever use is your so what is
happening because of the voltage drop
you can see the electrical barrier is
lowered and as a result the electrons
will move from the valence band to the
conduction band and as a result this way
there will be a flow of current so it
because of this it is the electrons are
moving from one band to another band
equivalency band 2 electron band on the
other side of the junction this is this
will lead to a flow of current and so
you can see the band gap is overcome
because of the electric field that is
being applied and this electrons will
move because of the positive voltage
applied on the drain and as a
consequence this current is become is is
not very small as the GMA
is gradually reduced as the geometry is
gradually reduced that electric field
become the across the diode cannot can
be substantial and it has been found
that this this current is dominating the
PN Junction leakage current that means
in deep submicron sub micron technology
that bt bt current band-to-band
tunnelling current is larger than the
leakage current so a lot of attention is
is focused on the for the reduction of
this band-to-band tunnelling current
okay so this is the main tube and
tunneling current now let us move on to
the I mean let us consider the equation
let us not go into the details of this
equation this is essentially say complex
equation derived from from the knowledge
of semiconductor device physics but from
this expression you can find out its
dependence on various parameters
obviously it has defined it as
dependence on the voltage it has
dependence on the mobility of the device
mass mass of the electron or hole and
charge and this is H is Planck's
constant so that means this current is
predominant I mean only for holes not
for I mean electrons not for homes so in
case of deep submicron technology high
doping concentration and abrupt doping
profiles are responsible for significant
bt bt current actually as you know
whenever we are going from one
technology to another technology the
dimensions are reduced later on I shall
discuss about it in more detail and but
to maintain constant field usually the
supply voltage is also reduced but to
maintain the electric field you have to
increase the doping concentration so
doping concentration is in is being
increased gradually and also the doping
profile is not very smooth abrupt
lowering profile because of
fabrication of a smaller dimension
devices and this is responsible for
significant band-to-band tunnelling
current went to banned tunneling current
okay so this is in brief discussion
about the band-to-band tunnelling
current and now let us focus on sub
threshold leakage current the sub
threshold leakage current is a very
significant component of the leakage
power and this current passes from drain
to source through the channel normally
we know that you know normally we assume
that for for vgs less than VT ids is
equal to zero that means there is no
channel if the gate voltage is less than
the threshold voltage and on drain
current will start flowing only when the
gate voltage is larger than the
threshold voltage of the device but in
practice that is not true particularly
when the gate voltage is increased from
zero and it becomes closer to the
threshold voltage there is significant
amount of channel current that flows and
that is known as sub threshold leakage
current because since it is occurring
for a gate voltage less than the
threshold voltage that is why the name
sub threshold leakage current so the sub
threshold leakage current is a
significant component of the leakage
current a current that flows between the
source and drain and here is the
expression for the sub threshold leakage
current a is a kind of constant
primarily depends on the fabrication
length width and various other
parameters then QB Q by n SKT and VG is
the gate voltage v s is a substrate
voltage and V t0 is essentially the
threshold voltage with zero body bias
zero bias of the zero biasing on the
substrate and this delta - vs is is the
is due to the to take into account the
body bias effect later on you will see I
shall mention about this body effect
when the substrate is not connected to
the source
if a voltage is applied it can be
positive body bias or it can be reverse
negative body bias whatever whenever the
body bias is really negative then you
will see that threshold voltage is
increased when it is positive the
threshold voltage will be will be
reduced and as a consequence it has
impact on the leakage current I have
already mentioned about this so this is
this Delta - is essentially the sub
threshold 2k 2k to take into account
body effect so this is known as body
bias coefficient and this this
particular parameter this is this this
particular parameter is to take into
account the effect of double effect then
- then - you know whenever you apply a
drain voltage double effect then drain
induced barrier lowering so so take into
account body effect and develop X this
is the expression for sub threshold
leakage current and as you can see here
also there is a dependence on the
temperature Q by K T and this current
increases drastically with temperature
and it is also increases at threshold
voltage is scaled as you know whenever
threshold voltage is reduced you know
this this particular current will
increase and whenever we do device size
scaling then threshold voltage is also
scaled that means you know let us
consider the situation suppose you are
reducing the dimension by a factor of K
then as you reduce the dimension by a
factor ik by K usually the supply
voltage is also reduced
by a factor of K VDD is begin a new VDD
is K P DD similarly the threshold
voltage is also reduced at the same
proportion sir kV T so it is also raise
a factor a reduction factor so as you do
that that means supply voltage is
reduced to keep the field constant and
as you do that to maintain performance
or you have to reduce the threshold
voltage but as you do that the leakage
current increases that means this this
this reduction in threshold voltage
leads to increase in leakage current
that is that is the reason why as the
device dimensions are reduced as you go
from one technology generation to the
new technology generation leakage
current increases because of the
reduction in the threshold voltage so
this this has to be taken into
consideration how we can really reduce
this sub threshold leakage current this
is a very important area
I mean point of concern and people lot
of people are concentrating on how the
this current can be reduced and in fact
one important direction is to use high K
dielectric so that the thickness of the
silicon dioxide layer is is larger so
using high K dielectric the maybe this
layer the leakage current can be reduced
to some extent but again this is another
I mean the one way of reducing the sub
threshold leakage current and the sub
threshold leakage current has dependence
on a number of parameters vary there are
various mechanism which continues
contributes to the sub threshold leakage
current one is your I have already
mentioned drain induced barrier lowering
nibble effect second is body effect
third is narrow width effect forties
effect of channel length on and Vth
roll-off and there is a impact of
temperature effect of temperature so let
us very briefly consider how the
threshold sub threshold leakage current
is affected because of these effects
first of all drain induced barrier
lowering in this particular diagram as
you can see I have plotted the lateral
energy band diagram at the surface
versus the distance so you can see here
this side is the source and the size is
a drain so here this is the Y by L
length is the channel length and so as
the length is I mean the on this side we
are going it is closer to the drain and
this side it is closer to the source and
the energy band diagram is shown now it
is not drawn for three different
parameters by varying the length L and
second one is by varying the drain drain
voltage VDS so first one is you can see
the length of the channel is long six
point two five micron and the gate with
the end voltage is also small point five
volt so in that case you can see curve
is more or less perfect I mean the
energy that energy band diagram is what
is what it should be and as a
consequence the the threshold voltage a
will be I mean you have to apply the
gate voltage higher than the threshold
voltage so that to induce channel
current and so on in other words the
threshold voltage is high and leakage
current will not be high on the other
hand as you can see in case of car B and
curve C curve B corresponds to 1.25
micron length is small and supply
voltage is small also and last one
the length is small supply voltage is
large that means whenever you have got
small dimension and large supply voltage
then you can see there is a significant
lowering of the bed
of the energy band diagram whenever
there is a lowering of the energy band
diagram what what happens you require
lower voltage to induce current and that
leads to reduction in threshold voltage
and as the threshold voltage is reduced
what happens the leakage current sub
threshold leakage current increases so
so we find that this is essentially
effect which is due to read of smaller
dimension of the channel or a lot
normally we call it short channel effect
this is one of the short channel effects
and it becomes predominant when the
drain voltage is large as it is evident
from this diagram okay so this is the or
drain induced barrier lowering and I
have already shown you the expression
for the drain current of the of that X
you know that this expression the sub
threshold leakage current where the that
VDS has been taken into consideration
the impact of daredevil attending this
very alluring second is the body effect
I have already mentioned about this
while discussing the threshold voltage
there we have seen that you know instead
of connecting the substrate to source
for example this is a n MOS type
transistor this is n plus n plus this is
the channel region here you have got the
gate this is the gate now here you have
got a P plus region which is normally
connected to source then it is grounded
so here this is a substrate is down dead
connected to source and then grounded so
in this case there is a zero body bias
now suppose you apply a negative voltage
to it with respect to source so then we
are calling it a reverse body bias
so you can apply a different substrate
bias voltage with respect to the source
and that we will actually change the
threshold voltage how it why it changes
I mean the expression is there but
physically what what occurs what is the
physical phenomenon actually as the
negative voltage is applied to the
substrate with respect to the source the
way to source Junction well to source
Junction the device is reverse biased
and both depletion region is widened so
the depletion region bulk depletion
region is widened that means this region
is there is a depletion region you know
this depletion region is widened so
whenever it is widened it becomes wider
obviously you will require a larger
voltage to be applied to the gate to
induce to induce a channel that means
the to overcome the depletion region and
to create to to form the you know that
inverse to create the inversion layer a
larger voltage is required in other
words threshold voltage is increased so
this is the that is the reason why
whenever reverse body bias is increased
threshold voltage is increased on the
other hand you can apply a positive
requires voltage to the substrate with
respect to the source in that case there
will be reduction in the threshold
voltage and both you can do but normally
to reduce the leakage power it is
essential to increase the threshold
voltage so you have to apply reverse
body bias on the other hand if you are
interested in increasing the performance
not the
not to reduce the leakage current then
you can apply forward body bias to
uniquely reduce the threshold voltage
that will improve the performance so
that also can be done but our interest
is to reduce the leakage current so this
is the body effect so you can see in
this particular curve the how the body
effect is changing the drain current so
here there is a plot off on the x-axis
you have got the gate voltage on the
y-axis you have the drain current in
logarithmic form so it is a kind of log
linear curve so y-axis log logarithmic
and Y x-axis linear that is that voltage
is linear now you can see when the zero
gate voltage is there even then there is
a current flow so there is a drain
current and that drain current when the
gate voltage is zero that means the
substrate is connected to the substrate
is connected to the source then you can
see this is the current whenever you in
P input increase the reverse body bias
is the the substrate is connected to
minus 1 minus 2 minus 3 minus 4 and
minus 5 you can see these are the
different curves and the lower tab
corresponds to a reverse body bias of
minus 5 volt so you can see for zero
gate voltage for different body bias how
the current is reducing so this current
is you can see what is the order of
magnitude difference roughly for order
of magnitude difference in leakage
current this is 1 into 10 to the power
minus 12 ampere and this is 1 into 10 to
the power minus 8 ampere so you can see
for order of magnitude of reduction in
leakage current is possible by reverse
body biasing so this particular curve
the shows the impact of body effect
on the leakage current sub threshold
leakage current coming to the narrow
with effect you know we have discussed
about the effect of the length now we
are considering the effect of the width
when the width is small that too has an
impact on the threshold voltage so here
we see how the gate with affects the
threshold voltage you can see when the
width is large of the order of say 2 to
10 micron you can see it has no impact
on the threshold voltage that means
threshold voltage is more or less
independent of the width so it does not
change but whenever it is small less
than 1 micron
less than a micron you can see
particularly when the when the gate
voltage is large the body bias is body
bias particularly when the body bias is
large there you can see there is a
lowering of the threshold voltage and
this lowering of the threshold voltage
occurs whenever the width is small less
than a less than 1 micron and you can
see the threshold voltage decreases
sharply so because of this narrow width
effect the threshold voltage is reduced
and that leads to increase in the sub
threshold leakage current and let us
consider the Vth role of you know
normally the gate voltage the you're
applying supply some voltage to the gate
also you are applying voltage to the
drain as you know to attract the
electrons from the source or you apply
positive voltage to the drain that is
how the current flows now let us have a
look at the channel region channel
region is shown here it you can see the
length is L from here to here
from if you consider from this point to
this point this is the lane but whenever
you apply a positive drain voltage
it creates depletion regions like this
these are the depletion regions because
of these depletion regions it is no
longer I mean if the channel and channel
length is no longer L in the lower part
of the channel so you can see it is no
longer a kind of rectangle but it takes
the shape of a trapezoidal and as a
consequence the effective area reduces
effective volume you can say volume of
the channel reduces so whenever the
volume of the channel reduces what
impact it has got now it has got the
impact of lowering of the threshold
voltage that means the area at the
volume is reduced that means he will
require smaller voltage to create
inversion layer in the channel and if
the volume is large then you will leak a
larger volume voltage to create the
inversion voltage in the channel and and
as a consequence what happens when the
channel when the channel when the
channel you can see when the channel
length is reduced you can see
particularly this is also a short
channel effect there is a kind of roll
off of the threshold voltage and this is
typically known as VT h0 log that means
ETH role of occurs when the channel
length is small and particularly device
dimensions are less than the very close
to the submicron region and as a
consequence the leakage current sub
threshold leakage current increases this
is the VT h role of coming to the
temperature effect we have and we have
shown you I have shown you the plot of
the drain current with respect to the
gate voltage and we have seen there is a
slope that slope is significantly effect
by the temperature and and this is known
as sub threshold slope so there is there
is strong dependence of threshold
voltage on temperature particularly the
sub threshold slope is affected sub
threshold slope St is represented by 2.3
into KT by Q into 1 plus C DM by C do X
these are essentially some capacitances
within the geometry let us not bother
about that
those are dependent on the physical
fabrication parameters but here you can
see the temperature is here and there is
linear dependence of sub session subsys
on slope on the temperature and actually
this plot will illustrate it as you can
see here I have drawn the same diagram
shown same plot is shown but for
different temperature here the gate
voltage has been kept fixed two point
seven volt and on this side on the
y-axis the drain current is plotted in
logarithmic plot and gate then gate
voltage in linear plot these are the
dead band voltages gate voltage s so you
can see at zero gate voltage these are
the different currents and the lower
curve corresponds to minus 50 degree
centigrade the upper curve correspond to
100 degree centigrade so you can see the
slope is changing as you are increasing
the temperature slope is changing and as
a consequence currently changing the
leakage current sub threshold leakage
current is changing here also as you go
from minus 50 degree centigrade to 100
degree centigrade you can see there is
about I think 6 order of magnitude
difference in the sub threshold leakage
current so here for minus 50 degree
centigrade for 4 point 5 into 10 into 10
to power minus 13 ampere and for 100
degree centigrade it is 7 point 6 7 into
10 to the power minus 9 ampere so you
see for order of magnitude rather 4
point 5 or 4 order of magnitude
difference in the sub threshold leakage
current that is occurring
so this is the temperature effect so we
have discussed about the various effects
there are on the sub threshold leakage
current now let us focus on the those
get you know kind of current through the
gate oxide tunneling through gate oxide
now why why do tunnelling occurs through
gate oxide the tunneling through gate
oxide is occurring because the thickness
of the gate oxide layer is gradually
reduced as you go from one technology
generation to another technology
generation length is reduced width is
reduced the thickness of the silicon
dioxide is also reduced in the present
day technology will be surprised to know
that sickness of the silicon dioxide
layer is nothing but few layers of
molecules and as a consequence what
happens you whenever you apply a gate
voltage that leads to tunneling of
current this is illustrated with the
help of this three diagrams here you can
see this is the flat band condition
where no voltage is applied to the gate
now
as you apply apply positive voltage to
the gate you can see this is the P
substrate and this side is the gate as
you apply a positive voltage the the
energy band diagram is lowered because
of this voltage applied to the gate and
you can see electrons is passing from
the substrate through the gate oxide
layer to the gate so tunneling of
electrons is occurring through the
silicon dioxide layer normally we assume
that silicon dioxide is a pure insulator
no current can flow through it but this
is not happening in deep submicron
technology because of this tunneling
through gate oxide and not only
electrons the holes can also pass
through the gate whenever you apply a
negative voltage to the gate but because
of higher mobility of holes
it is unlikely that the the holes will
pass through the gate XM in through the
gate oxide that means whenever you apply
a negative gate bias there is a
possibility that holes will also tunnel
through the silicon dioxide layer but
that usually does not happen primarily
because we normally apply a positive
gate voltage and because of lower
mobility of electrons they they tunnel
through the silicon dioxide layer so
tunneling of electrons to the N Mo's
capacitor with a heavily doped n plus
polysilicon gate and p-type substrate
that is shown in this diagram now there
is another you know gate gate leakage
that is known as hot carrier injection
you know whenever you are applying a
gate voltage may be whatever may be very
small but because of the smaller
thickness of the silicon dioxide layer
that electric field is so high that it
creates some electrons of very heavy
very high energy that means electrons
acquire very high energy those are known
as hot electrons those hot electrons
acquire so much energy they can pass
through this silicon dioxide layer now
that is what is happening in this
particular key case you can see the
electrons are passing passing through
the because of the high electric field
passing through the silicon dioxide
layer going from the substrate to the
polysilicon of the gate region so
injection of hot electrons from the
substrate to oxide due to high electric
field near silicon-silicon dioxide
interface because of smaller geometry of
the silicon dioxide so this is known as
hot carrier injection so these are the
two phenomenon responsible for gate
leakage one is your hot carrier
injection and another is your gate gate
induced drain leakage sorry another is
your tunnelling through gate oxide
coming to the another phenomenon that is
your g ideal gate induced drain leakage
now you know this happens because of due
to high electric field in that drain
Junction
you can see there is an overlap of great
gate and drain and here there is a high
electric field that leads to you know
those electrons you can see these
electrons are moving from this region
and going to the substrate and that
leads to current what is known as gate
induced drain your drain leakage and
this is due to a high electric field in
that drain Junction so these are all
arising out of a short length and high
electric field created because of
smaller dimension and even a small valid
a voltage can create large electric
field coming to the last phenomenon that
is punched through the punch through
voltage PPT okay let me briefly explain
what do you really mean by punch through
so this is the most transistor again I
am drawing say this is your say source n
plus n plus source so this is source
this is drain now whenever the and this
is the gate region here you have got
poly silicon layer Scylla silicon on top
of silicon dioxide now whenever you
apply a positive voltage there is a
there is a you know this is the
depletion region now as you increase the
drain voltage what happens these these
depletion regions widens and it may so
happen that depletion regions will touch
each other
this is known this this is known as
punch-through when the two depletion
regions touch each other and that point
we known as punch-through has occurred
and this points through voltage VP T
before the gate drain voltage when it
occurs estimates the value of the VD s
for which punch through occurs at vgs is
equal to 0 that means obviously this
punch through voltage is dependent on
the gate voltage as well when the gate
voltage is small
and finally this is defined as the punch
through voltage fan gate voltage is zero
and this is represented by this
expression v PT into alpha n B into L
minus WJ cubed so NB is the doping
concentration of the bulk l is the
length of the channel WJ is the junction
weight so points through increases sub
threshold current and degrades the sub
threshold slope so this is the impact of
the punch through and in this particular
diagram different types of leakage
currents that I have drawn explained are
shown a summary of that is shown here
for example this is the zero gate
voltage where there is a quadrant
current because of weak inversion that
is sub threshold leakage current and
Junction leakage current and then
because of the IBL effect then induce
barrier lowering and gate induce del
leakage current you can see there are
more currents
I mean currents are increasing so you
see so n channel current drain current
versus gate voltage lust rating various
leakage currents components are shown in
this particular diagram for different
drain voltages is the Sun and so you can
see that we can we can tell that this
leakage current is is very there is very
important and there are different
components and these components I have
explained in detail now let me conclude
with another very important point
particularly the leakage current you can
see the we have two two lines the top
one is drain current the bottom one is
leakage current or standby current you
can see the slope of this is larger than
the upper one that means the leakage
current is increasing at a faster rate
than the than the active current active
current or you can say dynamic current
now leakage current will be
significantly higher that will be more
clear from this particular diagram you
can see here for 0.25 micron technology
indicate leakage current is
insignificant but for 0.18 micro micron
it is visible it is significant
component of the active current but
whenever we go to point zero seven
micron that is your 70 nanometer you can
see the leakage current component is
more than the dynamic current component
that means leakage current leakage power
is becoming a large component of the
total power dissipation what is the
impact of that impact of that is you
have to reduce runtime leakage current
what you really mean by that earlier
people were developing techniques by
which you can reduce the dynamic power
when the circuit is in operation circuit
is active and leakage current was
reduced when the circuit was in standby
mode but now since the leakage current
component is a significant component of
the dynamic power when the circuit is
active it is in runtime condition then
also you have to reduce the leakage
current that means runtime leakage power
reduction is becoming a very important
research area in the present context
okay with this let me discuss about the
various degrees of freedom I have
discussed about different types of power
dissipation switching power dissipation
short-circuit power dissipation leakage
power dissipation we find from this
expression different parameters are
present which parameters are important
rather how can you really reduce this
power the power dissipation the first
and the most important one is the supply
voltage we find that supply voltage is
present in quadratic from in cubic form
or
linear form so in all these expression
supply voltage is common everywhere it
is present and that is the reason why
read supply voltage reduction is the one
of the most important technique that is
being used to reduce power dissipation
then of course physical capacitance CL
CI that has to be reduced then switching
activity alpha L alpha I reduction of
physical capacitance and reduction of
switching activity these two are to be
reduced to reduce the dynamic power then
threshold voltage reduction is necessary
particularly to reduce the leakage power
dissipation we have seen that leakage
power is has exponential dependence on
the threshold voltage so based on this
discussion I shall be discussing various
techniques of power reduction of I mean
fellow and I mean know for techniques
and they can be broadly divided into
three categories first was first one is
supply voltage scaling second one is
minimizing switched capacitance they are
essentially we shall be minimizing
capacitance value as well as the
switching activity and last one is
minimizing leakage power primarily by
controlling the threshold voltage so
from next class onwards we shall
concentrate on various techniques for
reducing power dissipation rather low
power techniques thank you
you
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