Noise Immunity & Noise Margin Video Lecture | Digital Electronics - Electrical Engineering (EE)

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in this video I will talk about noise
immunity and noise margin of our logic
gate while we are dealing with a digital
logic circuit the logic circuit may
encounter noise voltages from different
parts of our circuit if the noise
voltage crosses a certain limit or
specific limit the logic gate may
malfunction
so this arises to terms noise immunity
and noise margin in case of our digital
logic circuit at first I will define
this noise immunity and noise margin
after that I will show you two formula
to find out the value of noise margin
after that I will show you how to
calculate noise margin in case of TTL
logic family so what is this noise
immunity noise immunity is the circuits
ability to tolerate noise at the input
side let's say anyhow in oil voltage is
generated in our digital circuit the
noise immunity will indicate the ability
of our digital circuit to withstand this
noise voltage to measure the noise
immunity of a circuit we use a term
noise margin the amount of noise voltage
for which our digital circuit will
capable off to tolerate that noise
voltage will be known as our noise
margin now let me describe this noise
margin noise margin is a quantitative
measure of noise immunity quantitative
measure that that means I will calculate
the amount of noise voltage for which
our circuit will able to tolerate that
noise voltage C or the amount of noise
bike that the logic gate can withstand
so noise margin is the quantitative
measure of our noise immunity that means
it will measure the amount of noise
voltage for which the circuit can resist
that noise voltage and will not show any
false operation in our logic circuit
there are two values of noise margin is
specified for any logic circuit first
one is low level noise margin same one
is high level noise margin I will denote
low level noise margin with BN L and
high level noise margin with P n H so
how do we calculate this low level noise
margin c BN l is equal to b i l max -
pol max see here if i show the input
logic levels with a block diagram like
this and output logic levels with a
block diagram like this see low level
noise margin is p i l max when our input
is a logic 0 the maximum amount of
voltage that can be treated as logic 0
is known as bi
l max and the maximum amount of voltage
that can be treated as logic 0 is known
as e o L max if I take the difference of
VI L Max and vo l max I will get our low
level noise margin C this will be our
low level noise margin or the range of
voltage between these two will be our
low level noise margin what will be our
high level noise margin c pn h equal to
vo h minimum minus VIH minimum see when
our output is at logic 1 the minimum
amount of voltage that can be treated as
logic 1 is equal to P o H minimum and
the maximum amount of voltage that can
be treated as logic 1 at the input side
is known as PIH mean if I take the
difference of this Poh mean and PIH mean
I will get our p n h see the range of
voltage in this range will be our p n
H that means for high level voltage our
digital circuit will withstand any noise
voltage in this range and for low level
our digital circuit will resist any
noise voltage in this range and will not
show any false operation in our circuit
Illinois spike greater than the noise
margin may drive the gate into the
intermediate range and this gives rise
to ambiguous
in the operation of our logic circuit
that means if we have any negative noise
spikes less than this V in H that will
drive the gate into this intermediate
voltage range which will create an
uncertainty in the operation of our
logic circuit if we have a positive
noise spikes greater than this V n L
that will drive the gate into this
intermediate range which will again
create uncertainty in the operation of
our logic circuit now let me show you an
example of calculating noise merging for
our TTL logic family the table shows the
input and output voltage specification
for the standard TTL logic families
parameters vo
h1 output high minimum voltage is 2.4
volt typical voltage could be 3 point 5
volt and maximum voltage is not
specified vol minimum voltage is not
specified DPL voltage zero point 2 volt
and maximum could be zero point four
fold minimum voltage VI H minimum value
of this voltage could be two point zero
volt typical folders could be
typical no hello is specified mayhem
Holden is not specified de il minimum
voltage typical voltage are not
specified maximum voltage could be 0.8
volt we have to use these fellows to
calculate the maximum values of noise
spike that can be tolerated when a high
output is driving an input the maximum
value of noise spike when high output is
driving an input that means how we are
asked to calculate our P in H V n H that
means we have to calculate the maximum
value of noise spike that the circuit
could resist and will not show any false
operation in our given circuit and in B
we have to calculate the maximum value
of noise spike when low output is
driving an input low output is driving
an input that means we have to calculate
our P
in in low level noise margin to
calculate G n H and P n L I will use our
previous block diagram to calculate our
P and H and P n L C the maximum minimum
value of this Poh could be 2.4 volt and
the maximum value of this vol could be
0.4 fold that means I will specify Poh
minimum equal to two point four volt pol
max as zero point four volt PIH PIH
minimum would be two volt and VI L max
could be 0.8 volt I will set these four
fellows in our logic level diagram see
here VI H min equal could be two point
zero volt VI L max could be 0.8 volt voh
mean equal to two point four volt pol
max equal to zero point four volt which
implies that when an output voltage is
high the minimum value of this logic one
could be as small as two point four volt
when our input is at logic one the
minimum value of this logic one could be
as small as two point is zero volt and
you see that the voltage difference
between this vo h and p i h vo h minimum
and p IH minimum is known as our high
level noise margin c v n h equal to vo H
min help you Oh H min equal to two point
four fold and PIH min vo h mean minus TI
h mean here p IH min equal to 2 volt
which implies that our high level noise
margin will be equal to zero point four
volt this indicates that when our logic
circuit is at logic 1 the maximum hello
of the noise spike could be
0.4 volt for which the circuit can
withstand and will not show any false
operation in our circuit now our pn l c
here at the input the maximum value of
this logic zero which is known as pil
max could be as larger as 0.8 volt and
the maximum hello of the logic 0 at the
output logic level could be as large as
0 point 4 volt and I have shown you that
low level noise margin is the difference
of this pil Max and P o l makes here pn
l ik will be equal to vi l max which is
equal to 0.8 and here p o L max equal to
0.4 which indicates that P n L will be
equal to 0.4 fold this implies that when
our circuit is at logic 0 the maximum
hello of the noise bike could be 0.4
volt as the noise is a random signal
therefore it will take a shape like this
this is a spike and the mess envelope
the noisy spike could be 0 point 4 volt
and for maximum that amount of voltage
our circuit will not show any false
operation
see here I have calculated DN h equal to
vo H minimum minus VIH minimum equal to
two point four - to hold zero point four
volt and DN l equal to this is low level
noise margin g IL match - vol max 0.8
minus 0.4 fold equal to 0.4 volt okay
that's it
thank you