NOR & NAND SR Latch Video Lecture | Digital Electronics - Electrical Engineering (EE)

[Music]
hey what's going on guys done Maya for
simple snippets and welcome back to
another video tutorial on sequential
circuits logic gates boolean algebra and
digital electronics as a whole so in
this video tutorial we will be looking
into the SR flip-flop also known as SR
latch and in the previous video tutorial
we saw the concept and basic working of
flip-flop and the fundamental principle
that it works on and how it stores one
bit memory so if you have missed that
video you can check it out and with that
being said let's get started with
today's topic so in today's topic as you
can see on the screen we have a
flip-flop which is known as SR flip-flop
and this SR flip-flop is one of the most
basic flip-flops and we'll see the
mechanism and it's working we'll also
see the circuit diagram block diagram we
will actually practically see all the
different cases and the input and output
and we also chart down some truth tables
now this SR flip-flop can be constructed
in two ways that is using nor gates and
NAND gates so we are going to be using
both of these so in this entire video
tutorial series you'll understand
everything about flip-flop so make sure
to watch this video till the end of the
video tutorial so we will start off with
a little bit of theory
so SR flip-flop as the circuit series
has two inputs S which stands for set
and R which stands for reset and it has
two outputs that as you can see in this
diagram Q and Q Bar and it consists of
two nor gates and even NAND gates can be
used so we are going to see both the
circuits so first we'll start off with
nor gate construction circuit diagram
and then we'll start off with the NAND
gate and it is connected enough feedback
mechanism and feedback arrangement so
this is basically the crux of sequential
circuit said that the output is given
back as a feedback to the input and
that's how it is down termed as a
sequential circuit okay so let me just
first start off with the circuit diagram
so we have two inputs you can see s and
R over your now these nor gates are
arranged such that the output of nor
gate one so let's say this is nor gate
one and two output of nor gate one acts
as one of the input of nor gate two and
output of nor gate to access one of the
input for nor gate one also they have
their individual inputs SNR so basically
this is a to Grid nor gate right you can
see the output Q and Q Bar which in most
cases should be complement to each other
and those are the two stable
put so again it is used to store a 1-bit
memory and it exists in two stable
states hence it is a bi-stable device
and the two stable states should be high
and low and in SR flip-flop the two
stable states are called set and reset
that is the that's why the name s R so S
stands for set and R for he said also
known as SR latch because it acts also
acts as a latch which means that it can
store a memory when I say latch it means
that state which basically stores that
memory and holds on to the data and we
will also see that in the cases so
starting off let's take a little bit of
background info on nor gate so this is
the truth table for an or gate you can
see only when the both the inputs are 0
0 the output is high otherwise all of
the outputs are 0 for all the
combinations of two input nor gate we've
already seen nor and NAND which act as a
universal gates and I have separate
video tutorials on both so if you can
check it out in this playlist also I
will drop some cards and you can see a
card on the top right corner as well if
you want to see in detail so yeah this
is the table for basic nor gate or 2
input nor gate which we use when we
actually derive the cases so you can see
I have 2 tables as well which we are
going to practically solve and fill out
ok so now what we will do is we will go
through full different cases of this SR
flip-flop and the reason why I'm going
to go ahead with 4 different cases is
because we have 2 inputs and the
combinations or the unique combinations
would be 2 raise to 2 which is equal to
4 so that is 0 0 0 1 1 0 and 1 1 right
so each of them we are going to consider
as case so for case 1 what we are going
to do is we're going to say s is equal
to 0 and R is equal to 1 ok so I'm going
to say s is equal to 0 and R is equal to
1 for the first case so let's start off
with the upper nor gate so when this is
0 if you see the truth table we cannot
actually predict the output because one
more input is supposed to be coming over
here but if you observe for R whose
value is high so one of the input of the
nor gate is 1 and if you see the table
of the nor gate if any of the input is
high the output is always going to be 0
so irrespective or regardless of this
input so we don't need this input we
just need only 1 input which is high and
once we found out that one of the input
of an or gate is 1 the output is always
going to be 0 so this is coming from
basically the truth table that's why I
have drawn the table
you can see over here so we don't need
to know what input is coming into this
circuit line we just need this circuit
line which is high and we can directly
see that the output is going to be zero
so your Q is equal to zero right this is
the output which is going on the Q line
now this Q is fed back as input to the
upper nor gate right so it's going over
here you can see so this zero is fed
over you're now svv assumed already zero
and there is one more zero coming in
from your so this is that case so the
output is going to be one right so Q Bar
is going to be one now Q and Q Bar a
complement to each other which means
that this is a stable state and this
state is known as reset and the reason
why it is called reset is because R is
equal to one
it's not depending upon the output since
R value is one it is known as reset now
let's take a look at case number two now
in this case we are going to say s is
equal to 1 and R is equal to zero so s
is 1 over here and R is 0 over here ok
now again going through the table of nor
gate if any of the input is high which
is the case for the upper nor gate the
output is always going to be 0 this
comes from the table right so you can
directly write 0 over your so Q bar over
here is going to be 0 now this Q Bar is
fed back as input to the lower nor gate
right over here so we are getting 0 0 so
0 0 is this first case which so the
output is going to be 1 so Q is going to
be 1 so s is equal to 1 Q is equal to 1
this state is known as STP that is said
state okay let's see case number 3 now
here what we are going to assume is s is
equal to 0 and R is equal to 0 so I'm
assuming s is equal to 0 and R is equal
to 0 now in this state you're not able
to actually find out the or guess the
second input for both the nor gate said
so in this case what we're gonna take is
the previous output that is the state of
the previous output which was this state
set state right
so Q was 1 in this case so I'm going to
assume 1 over here so 0 + 1 is going to
give me 0 so Q Bar is going to be 0 and
then this 0 is again fed back over here
which gives me 0 and 0 which is this
case which gives q is equal to 1 so what
did we get over here you can see that
when we assume s equal to 0 and 0 the
previous output Q equals to 1 and Q Bar
equal to 0 was supposed to be considered
and was considered because it was
supposed to be fed back in the norm
it for a result right and then we got
the same output that is Q is equal to
one and Q Bar equal to zero which is
exactly equal to this right so these two
cases are equal so that is why this is
equal to 0 and R equals to 0 is known as
latched state which means that the data
does not change or the output does not
change even when s equals to 0 and R
equals to zero now s equal to 0 and R
equals to 0 is essentially what we are
doing is we are cutting the power of all
we are setting both the inputs as 0 but
still the output is retained as q equals
to 1 and Q Bar equal to 0 which was our
desired output in the previous state so
it is also known as latch state or
previous state okay sorry for my
handwriting and I know it it sucks but
yeah that's that's that's how I write
anyways now we are moving to the last
state which is s equals to 1 and R
equals to 1 so I'm going to say s equals
to 1 over here and R equals to 1 so you
know if any of the input is high the
output is always going to be 0 but here
you can see that in both cases I have
assumed 1 so in both cases the output is
0 0 now this is contradictory because Q
and Q Bar cannot be same it has to
always be complement to each other so
when s equals to 1 and R equals to when
there is a contradiction and that's why
this is an unstable state and also known
as a race condition ok so this state is
always supposed to be avoided so that's
why you do not ever give s equals to 1
and R equals to 1 which gives us an
unfavorable output and it is known as a
unstable or raised condition so these
are the four different variations so now
we can actually fill out the table as
well so the truth table values are 0 0 0
1 1 1 0 and 1 1 now for 0 0 you can see
it is the latch state right
this was the third case so whatever
previous value we got for Q and Q Bar is
going to be repeated over here so I will
say Q n minus 1 Q Bar n minus 1 which
means that the previous state output is
again repeated okay for s equals to 0
and R equals to 1 so this is the reset
state that is the for state the output
was 0 and 1 for 1 0 we got 1 0 and for 1
1 it is a race condition so I'm just
gonna mark X over here so this output
cannot be predicted and it is unstable
now this this is one more truth table
which is basically giving you the next
state so let me just fill it out and I
will explain
so again 0 0 0 1
1 0 & 1 1 so 4 0 0 you are getting pre
wasted no this is next state QN plus 1
so 1 minus that would give us Q n right
so this is the previous state for 0 1
that is reset the QN value that is the
next state of Q so we are looking at Q
you have naught Q n bar or not not Q bar
that was getting a 0 for s 1 and R 0 we
are getting 1 and for this we are
getting a race condition so you can also
write it as race condition or an X or
something make unstable or something
like that so this is the basic working
of an SR flip-flop which is constructed
using nor gates so we also have a block
diagram which I did not mention earlier
so this is how the block diagram looks
like we just have a square inside which
you can write down SR latch and then you
can see the inputs SNR and the output Q
Bar and Q okay so nothing fancy here
it's just a block diagram but inside
this block diagram we have this kind of
functionality okay so this was SR
flip-flop using more gates now let's
take a look at SR flip-flop using NAND
gate okay again the same scenario what
we are going to do is we are going to
see the circuit diagram we're going to
see the block diagram we are going to
calculate the for different cases in
this case also because we have two
inputs here also so we will be having
four different cases right you have the
NAND gate through table and then you
have got construct these two two tables
so again the arrangement is pretty
similar just instead of nor gates we
have NAND gates and in the previous case
we had SR over here but the output is
flipped that is we had q bar over your
and Q or in the previous one but since
you are using NAND gate the cases are
going to be little different
so for 1 0 we are going to get Q Bar as
1 and not Q as 1 which is exactly
opposite to the previous one so I'll
show that when we actually drew the
cases ok so let's start off with proving
the different cases and for case 1 what
we will do is we will take s equals to 0
and R equals to 1 okay so we are
considering s equals to 0 R equals to 1
right so now check out the NAND gate
truth table you can see if there is any
0 which is in these three cases if there
is any 0 the output is always 1 only
when the input has both ones or all of
them are 1 the output is 0 so by this we
can easily say that if the input that is
1 circuit line going in the NAND gate is
0 regardless of what
that is 0 or 1 the output is always
going to be 1 right so we can directly
assume that so this means Q is equal to
1 now this Q is again fed back over your
to the second NAND gate so I can assume
this one and you can see R is 1 and one
more 1 is coming in this circuit line so
this is taking two inputs so this is the
last case so the Q Bar output is going
to be 0 so again since R is equal to 1
this is known as a reset state so it
doesn't depend upon the output it
depends upon which of the input is high
if s is high it is set State if R is I
it is research Neil let's see the second
condition or second case s equals to 1 R
equals to 0 so s is over here 1 R equals
to 0 so if one input is 0 we can easily
calculate the output as 1 for the lower
NAND gate this goal is a input to the
upper NAND gate and 1 and 1 you can see
this is case so the output here is going
to be 0 so we got Q Bar is equal to 1
and Q equals to 0 this is set state
because s is 1 let's see the third case
where in now we are considering s equals
to 0 and R equals to 0 just like the
case that we considered for nor which
was giving us the latch state rate it
was given as the previous output but
let's see what happens in this case when
we are considering s equals to 0 and R
equals to 0 so s equals to 0 and R
equals to 0 right so s equals to 0 then
regardless of what input is coming over
here we can easily assume this as 1 and
similarly for this also we can assume
this as well but now you can see again
there is a contradiction that Q and Q
Bar both are 1 which means that this is
an unstable State so in case of nor gate
in case of the SR flip-flop with nor
gate when s was 0 and R was 0 it was
giving us a latch state but but in this
case we are getting the unstable state
that was get that was coming in the nor
gate when we are giving input as 1 1 so
this is going to be a race condition and
this is a unwanted output and we have to
prevent this kind of input so when we
are using SR flip-flop using NAND gates
if you give the input as 0 0 it is going
to give us a race condition which is
also known as unstable condition so
moving on to the last state that is s
equals to 1 and R equals to 1 so this is
but obvious now this is going to give us
a previous state because this is the
only one case remaining right so let's
assume that so s equals to 1 and R
equals to 1 again
so now we have to assume the previous
state output so I'm not including third
stream because it is erased unstable
state for your you can see Q was zero in
the second state so I'm assuming this as
zero so this 0 goes over your so 1 and 0
you can see 1 and 0 will give you 1 so Q
is equal to 0 and Q Bar is equal to 1 so
this is the latch state latch or
previous state
okay now this previously it was this
state if the previous state would have
been reset then the same output would
have come over here so this is where the
flip-flop acts as a latch and stores
that memory bit
so now let's quickly fill out the table
it is pretty similar to what we did for
the nor gate so assume the inputs 0 0 0
1 1 0 1 1 can I will fill it although
here also
now let's see the output for 0 0 we are
getting a race condition so I'm just
gonna mock x over 4 0 1 that is a reset
state we are getting Q equals to 1 and Q
bar 0 for reset state we are getting 0 1
and for 1 1 we are getting Q n minus 1 Q
Bar n minus 1 which is the previous dude
again this state diagram wherein we are
or the state output wearing we are just
interested in the next state or the cube
Q value and not the Q Bar value so for 0
0 we are getting erased condition so NC
raise / X or an unstable or something
like that for 0 1 which is reset we are
getting Q equals to 1 for 1 0 is 0 and
for 1 1 now this is for next state that
we are calculating that is the latest
state that is n plus 1 so for 1 1 we are
getting QN which is equal to QN plus 1
minus 1 ok so that's why QN that is the
previous state so this is SR flip-flop
using NAND gate and you can see the
block diagram of the NAND gate now you
can see the output is just flipped over
here so s R and then you get Q and Q Bar
that's the only difference
so this is a basic block diagram but
inside this block diagram we have this
circuit arrangement you saw the circuit
diagram we saw that for different cases
and we also constructed all the 2 tables
so yeah that's it for this video guys
I hope you understood SR flip-flop using
nor as well as NAND gate we also saw the
circuit diagram we saw the different
cases and we also constructed the truth
tables so if you liked this video give
it a thumbs up share it with your
friends and if happens with subscribe to
this channel make sure
subscribe in this channel so that you
get notified whenever I upload a new
video tutorial so I'll talk to you guys
in the next video peace