Pipeline Hazards Video Lecture | Computer Architecture & Organisation (CAO) - Computer Science Engineering (CSE)

okay today we are going to see the
pipelining and Azores and after na means
under assistant professor Department of
CSE so what is pipelining I want to take
a case study of building a car when it
is unpack lined okay so see these up
jobs that is we are going to add a
factor a car okay so it takes 24 house
to manufacture a car and it is a
sequential execution how we are going to
differentiate either pipelining so when
you take your it is a nun pipeline it
takes 24 hours for manufacture in a
single car and after that we are going
for the next 24 hours of the next car to
manufacture so then we calculate the
throughput and so you take so one car
per 24 house and so when we are going
for parallelism how we are going to
improve the performance so when you see
the pipelining concept we are breaking
the job into smaller stages that is the
same concept we are going to use for
program execution
so consider here ABC we are enough
action in your car we are splitting it
into smaller stages when you see a that
means and continue the engine alone and
then one faction in the body part that
is the beat and then we are going for
painting that is see right so here in
pipelining we are splitting the job into
smaller stages initially we have seen
all the three parts we are making 24 us
so this take along only a task and then
her body part similarly again a task and
painting again a task
so it takes 24 a spurt we are splitting
the job it into smaller stages so once
the engine part get over okay so that
person who is allotted for it will be
free so we can give and manufacturing
the engine part 40-second so that's why
we are telling it in the second row a we
are going for in
Manufacturing at point-a similarly once
the body parts of the first car is get
over here we are just alerting for be in
the second for the second car and
similarly for see when we do such things
okay so the throughput now we are taking
it is like per car what they ate us so
three cars can be done and at the palace
and so but initially we can do only one
car because it is a sequential manner
after finishing the one particular car
manufacturing type then only they are
going for the next car for manufacturing
but when we split into jobs once the
engine person a manufacturing person is
free they can alert the second car for
manufacture of the engine so we can
reduce their time and we can improve the
performance now we are seeing the same
concept in and in section execution when
it is untied
okay so we have different stages like
fetching the instruction and decoding
the instruction and finally we have to
go for execution executing the in
succeed then we are not splitting into
jobs that is secret ship after finishing
the in session want to get executed then
we are going for the next sensation
right so this is how we are going for
unfine plane okay but when we go for the
pipeline concept here you can see the
same concept of your manufacture in the
car here ABC we are breaking the job
into smaller stages that is fetching
will be done at the clock cycle 1 and
then decoding anti clock cycle 2 and the
execution ok so that stage will feed the
clock say 2 3 ok so once the fifth cycle
get over at the clock cycle 1 it will be
free okay so we are just fetching the
second instruction at the clock cycle 1
we are pitching in season 1 but at the
clock cycle 2 we are fetching the second
and section at the same time we are
doing finally we are going for decoding
of the
right so this is the pipelining concept
once that stage is free we are alerting
the other instruction to all of the
houses okay at the crowd cycle 3 we may
see three in section okay it is in panel
that is fussing section is doing
execution the second section is doing
decode and third and section is doing
the execution so this is how we are
going to reduce the number of clock
cycles by weakening performance in I
play tape at the clock cycle 3 so now
when we compare the throughput we can
see in untie blind okay so that is the
clock speed so that is a 1 by 3 ms that
is we are going for a 3 number that
means 333 megahertz and so this is how
we are having an untied plate but when
we come for a pipelining okay so you can
increase to one gigahertz so we are
improving the speed clock speed then we
go for the pipelining because three
stages doing serially non pipeline but
only one at the time so we are improving
the performance so now we will see about
the hazards so till now we have seen
about how we have improved the execution
of in section performance by means of a
pipeline but there are some hazards will
occur in some times when we go for
pipelining we will see three types of
hazards that is the structure lazar okay
that is the different in section in
different stages conflicting for the
same resource sometimes the resource
conflict occurs due to the memory RQ to
the registers what we are going to use
that you will see in the coming slides
and data hazard okay so an insertion
cannot continue because it needs a value
that has not it been generated by an
earlier in section sometimes this will
occur in so that is the data hazard that
will occur to you - not providing the
data correctly and control hazard that
is it can fetch
continue because it does not know the
outcome of an earlier bit subject the
brand sensation accuracy so that is the
time the program counter value will be
incremented as normally by the
sequential execution but when the branch
at section occurs they have to increment
the program counter value according to
you okay so we have to decide whether
brand sensation to be taken or not so
that takes time how we can resolve the
issue right so these are the types of
hazards we are going to see and how we
are going to solve the data hazard by
means of forwarding and bypassing and
how the controllers are by branch delay
slot and structure Lozada game we will
go for some other technique how to
resolve it okay so first we will see
about how the Hazara occurs and then we
will see how these hazards can be
removed he came for into with the better
performance in pipelining
so first structure lozad then I see the
a five-stage pipeline
okay so initially at the clock cycle 1
we will not fetch the instruction ok so
in the next is a decode part ok and also
we will fetch all the operands that is
required and at the clock cycle 3 we
will go for the execution that is done
by the ALU and at the clock cycle 4 we
will go for storing the data into the
memory and clock cycle file again store
back the result into the registers
according to the in section what we are
going to give right so these are the 5 5
stage pipeline so here you can see from
the diagram you can see the memory we
are using a clock cycle 1 and also at
clock cycle 4 and also similarly we are
using the register at the clock cycle 2
and at the clock cycle fine so easily
you can understand when we go for
pipelining surely there will be some
conflict occurs are you using the
resources like memory ACK which is this
let us see how we've got conflicts so at
in section 1 okay so we are storing the
result at the clock cycle 4 ok so that
is the data memory we are going to store
the result into
so why we are denoting at the in section
one at clock cycle cc1 is I am and since
he for his diem means we are going to
fetch the in section from the memory
that is CC 1 and storing the data into
the memory so that say we are given it
as I am and DM respectively right so now
when we see at the in section 4 up to 3
in section getting execution there no
problem for no conflict occurs but when
you see at the in section 4 to get
execute that is the time we are fetching
the instruction from memory at the same
time at the clock cycle for the
instruction 1 we are storing the result
so in the data into the memory so that
is a memory conflict occurs so this is
called a aza ok so we can't proceed at
the in section 4 to face so what we are
doing is we are just sending the bubble
ok so bubble means we are not doing any
useful information during that
particular clock cycle ok so when we go
for a TM ok so that is the in section 2
ok so that is the time again we are
storing the result into the clock cycle
5 I think so clock cycle 5 that is the
time again I think so the conflict
occurs the in section 4 cannot be done
in that particular time so again we are
going for bubble right so similarly at
clock cycle 6 if we try again the in
section 3 get conflicted we can't fetch
the in section at the clock cycle 6 so
this is how the in section 4 get delayed
so the 3 in section we are making a
pipelining good ok and the next three we
are making a bubble if we can't proceed
further so that is though we are going
for and finally when we go for at the
clock cycles of it we can resolve the
issues ok so we can clearly say how the
performance is degraded so we can say
the 0.5 so first 2 3 in section is get
pipeline and the next 2 3 section it is
not yet by great ok so this is how the
consequence
a pipelining concept occurs 3 & 6 it we
are getting pipeline and then 3 bubble
and then 3 section of our pipe this is
how the performance ok of the pipelining
tgreider so how to resolve this issue if
we provide it for in section fits that
is I am and data to be stored into the
memory that is DM if you made it if you
make a separate memory for this we can
resolve the issue but it will be more
costly based upon the architecture okay
so they currently they will to resolve
this structure less or they will use a
separate memory for in Section H and to
store the result into the memory to
resolve this issue okay
and the register file access and so now
we till now we have talked about the
memory
I think the instruction memory and data
memory and how the conflict occurs and
how we resolve the issue now we will see
about the register file access all these
ridges of my license as I told you the
register read and write also happening
that results to the conflict in the our
clock cycle too but the in Section 1 add
that the clock cycle file we are using
the register so how we can resolve the
issue so what we can do is at the clock
cycle - we are making it into two parts
okay so you have the clock cycle - we
are making it into two parts
okay so that is one is decoding part
will takes place another one is read
okay so that say we are making at the
clock cycle - when you see the diagram
okay the second portion is in dot and
the first question is saying dot read
but when you see in the clock sacred
file okay the first portion is in dark
and the second portion is dr. okay so
what it actually means is the register
read will take place at the right part
and the register write will be taken
place at the first one okay so this is
how we have divided the two parts in the
register to show register read and write
happening at the same clock cycle but
also there is no conflict okay so during
the clock cycle file when you see the in
section one
so the register right will be taking
place at the separate core that is the
first part as mentioned in the diagram
and when you see the in section 4 I 4 ok
the second part that is the register
read will takes place the first part the
decode only will takes place so during
the decode part ok so the register will
be free so that is the time we are
alerting one register week right so this
is how we can resolve the issue in
resource conflict of registers of
register read and write happening at the
same clock cycle I cut it so this is how
we can solve the issue ok so there is no
conflict occurs during the clock cycle
fine so till now we have seen about the
structural hazard and the resource
conflict occurs due to the memory and
the registers and we have seen how to
resolve the issue now we will go for the
data Hassan as I told you the data is
all subjective you can't provide the
data for the further in section at the
correct time that leads to us on how to
resolve that issue so for example in the
in section I want okay so that is R 1 R
2 other two registers as an input we are
going to use and we are going to store
the result into R 3 so that is how we
are going to do it and when you see the
in section 2 here we are going to use
two registers that is r3 and r4 it so
when you see here we are going to give
an input r3 and r4 at the clock cycle
for for the second in section but we are
going to get the result of the first in
section of our three at one Liat the
clock cycle CC 5 right so that leads to
an Asif okay so the right writing of the
result of r3 only at the clocks I could
find okay but we are going to read fits
the operand r3 at the clock cycle 3
itself for the second instance that
leads to an observed because when the
series of instruction to be executed
okay so once the first in section r1 and
r2 result storing it into r3 okay so
that result only have to be used for in
section
- right so this list leads to the hazard
we can't provide the correct output of
r1 plus r2 talking an updated
information into the second section that
leads to a puzzle in how we are going to
solve
ok so register read r3 will be taking
place so we will go for register rename
it register renaming for that particular
thing to solve the issue and so that is
one of the part and try to do the in
Section r3 plus r4 at the clock cycle
for that also the conflict occurs
because we are getting whenever you
served in clock cycle 5 ok so here also
we can't read at the clock cycle for it
so now we are here again renaming it as
RA plus Admiral try it ok and the next
is when we go for at clock cycle fight
okay so the in section r3 plus r4 if you
try here ok so this is the time if it
comes okay so that take the conflict
will not occur so if it is a coming at
the in section 2 we have renamed as or 6
when we when it comes at in section 3 we
have named it as r8 ok and when we
commit at as in section 4 okay so that
is that time okay though we will check
for whether any data conflict occurs
here we can provide because the first
portion of the clock cycle file for the
first in section in section 1 ok we will
write our 3 okay and we can provide them
very clearly
okay we can provide a very clearly at
the in section 4 the second code that is
the register read r3 going to happen so
this is how we can resolve the conflicts
so we are just in the diagram you can
see right happens for the I in section 1
that is at the first part and read r3 ok
so now we will get that updated result
of heartily so we can we can solve the
conflict of data okay output of r3
we can resolve it
right so till now we have to provide
bubble okay because we be got an updated
information of our three only at the
cloud safe to find right so until that
time we should not do any usually
information that is so we have to we
can't proceed until the in section at
clocks I think fight right so when you
see here okay so when you see in this
diagram okay so every time we have to
see the first part is a decoding part
and the second part is register read
okay occurs okay so this is how we will
check the conflict whether any updated
information occurs among whenever the
data dependence occurs we have to solve
the issue only by seeing it whether any
data dependence at this or not okay so
now when we go for the control Hossam in
control hazard how we can resolve the
issues so here we can see when the
branch in section address and the branch
sensation occurs we will check the
branch in section whether the branch to
be taken or not okay so here there is a
problem at this so in the normal hazards
okay normal sequential in Section to be
fetched in a pipelining the program
counter value will be incremented by
four that means the next in section to
get executed but here if the branch in
section occurs we are seeing that the
processor have to go and which the
hundredth location so automatically the
program counter value have to be
incremented by hundred so that is that
time the hazard occurs because the clock
cycle to the second instruction will be
fetched and try to execute but we will
get only during the execution time the
branch in section occurs and we have to
change the program counter value by
hundred right so that is how the
conflict occurs that is called the
controller zone the controllers are
mainly occurs whenever the branch
instruction occurs during the execution
time only we would know and but we will
try for decoding the next section
right so when the control hazard occurs
so here you can see okay so are the
decode and the register read at the
clock cycle - that is the time again we
will know it is the branch insertion but
initially the program counter value will
be incremented by four okay but here now
only we will know we have to increment
by hundred because the branch sensation
occurs okay so initially the second
instruction will be fetched our as it is
in pipelining okay if not knowing that
it is a branch instruction okay once the
first in section get fetched we will
fetch the second in section try to
execute the second in section but the
processor have to go to the location
hundred because it is a branch in
section but we will get only at the end
of the clock signal - right so now we we
should not do Fitz are the fidget in
section okay as it is that should not be
executed so what we have to do is we
have to store the result okay so the
value of a program counter which is
incremented by four but we have to go
for program counter value which is to be
implemented by hundred as it is a brand
sensation we should not execute the
second instruction okay so what we have
to do is we are going to use okay so
when you use a technique here for each
branch install let me introduce a stall
cycle okay so that is a branch is
not-taken and start fetching the nesting
section the branch is taken need
hardware okay so there is two options we
have a conditional branch means whether
the branch to be taken or branch is not
to be taken so we are left one
particular in section after the file
stage pipelining it executed okay we are
just stopping and we are going to decide
whether to take branch are not to take
right so that will be a delay slot at
this okay so we will see the coming
slide how we can resolve the delay slot
but before that you should know okay
the second in section which is trying to
it is fetched and trying to execute okay
so that we have to stop so that say we
need a software that is the very
important okay so the predict is wrong
when you see the slide if the prediction
is wrong cancel the effect of the wrong
for thin section okay so we have to
cancel it and the fits the next in
section so branch delay slot have to be
done and executed anyway the in section
turns out to be of the correct path you
should work was then the insulation
turns out to be the wrong path
hopefully programs it is not lost so we
have to stop with the branch instruction
occurs we will stop it and we will have
a time whether the branch in session to
be taken or not taken that is the
biggest which alibi so if it is not
taken then the normal flow we need okay
so that's way we should not delete the
original flow of the in section so we
have to copy the in section that is the
program control which is a incremented
by for having that information have to
be stored it into the particular
location and we should not delete it
okay so the prediction is not taken okay
so that is the time we have to use that
normal flow okay if the branch friction
that is the branch to be taken then we
have to go for the new set of
instructions to be executed okay so this
is how the software take part in a very
important role whether to branch to be
taken or not taken according to the
execution of the branch in section right
so how to resolve the branch delay slot
so during the branch delay slot okay so
whenever the branch sensation to be
taken or not taken the delay slot occurs
we have to make a bubble in order to
resolve the delay slot that is the time
we can give provision okay so when we
are do some usual information during the
delay slot that is the time also we have
to check okay so when you see in this
particular slide okay so from the first
diagram you can see ok the delay slot
occurs after the branch in section
whether the branch to be taken or not
that is the time the previous in section
you see it is a it is now data it is not
a data dependence okay because we are
not going to store the result into r2
when you see that D and r1 comma R 2
comma R 3 okay and when you see if R 2
equal to 0 okay so when you see R 2
equal to 0 then the delay slot okay so
here when you see here are 2 is used as
a money input okay for a D ad in section
okay so that in section can be put after
the branch in section so it is not data
difference we can clear into thing okay
when you see the second condition that
if R 1 equal to 0 then the delay slot
occurs okay so that is the time it will
check some the previous in section
whether we can rearrange or not we can't
use a d ad R 1 because he said we have
to make the country rigid because after
doing D ad R 1 comma 2 comma 3 then only
we can go for checking the condition
right so but we can see the previous in
section that is d sub R 4 come out of a
coma R 6 so it is not a data dependence
so that particular in section can be put
after the branch in section got me point
so this is how we can resolve the issue
and you see the third thing also you can
see if R 1 equal to 0 then ok so then it
will in the branch in section ethnicity
it will see the previous thing so here
also data dependent circles
ok so that is the result have to be put
it in R 1 so we cannot rearrange it so
here also we have to we can see the next
sensation that is what okay that is our
7 or 8 at 9 that is not difference with
the R 1 equal to 0 so we can follow the
in section right so this is how we have
to solve the issue of delay slot so in
order to improve the performance we can
rearrange the in session which is not
data dependence it so thanks for
watching till now we have seen about the
pipelining
we are improving the performance of
that we are going for three types of
buzzards tax laws or datas are at
control Assad and we have seen out we
can to salvation thanks for watching