I/O Addressing Video Lecture | Embedded Systems (Web) - Computer Science Engineering (CSE)

input/output addressing hello students
as we have studied introduction to
input/output devices every input/output
device is controlled by writing some
command code to the control line the
zeros of the various input/output
devices like busy already can be
obtained by checking a status register
so pretty nun inputs are to advise
essentially very similar to reading and
writing memory I said that right
operations to the command register who
made the input/output device do a
certain operation just like memory
input/output devices need to be assigned
a unique ID or address but we need some
mechanism that can differentiate between
an input/output address and memory
address so addressing various
input/output devices through addressing
schemes are needed and they are as
follows one standard input/output
which uses specific input output
instructions to memory marked inputs
outputs which uses general-purpose or
brand manipulation instructions
currently only the Intel Pentium CPU
processor uses standard input/output all
other CPUs s PARC PowerPC alpha and
minimal use memory mapped input/output
let us discuss these addressing schemes
in the two that is target standard
input/output in the standard
input/output technique input/output
devices and memory location have
separate address spaces
Zeus versus are separate if there is an
external or explicit Sigma that
identifies the space let's take an
example to understand this concept
there are many low two games in the US
if we have a big game ticket with the
numbers one two three four five six and
the little salt draws the six winning
numbers one two three four five six then
although your big game ticket has the
winning numbers
you are not arena similarly whenever the
CPU sends an address one two three four
on the address bus that address can be
used to address a memory location or an
input/output device the CPU has an extra
explicit signal that indicates whether
the address is a memory location or an
input/output device the M req signal is
used through signal memory request the
io r eq signal is your true signal
input/output request when the CPU wants
access or read or write a memory
location it says the M req signal
similarly when the CPU wants to access
or read or write and input/output device
it says the IOR EQ signal the assembler
programmer who programs the CPU must
therefore have three different types of
assembly instructions to use this
disposer that allowed them to send the M
req or i/o req signals in the Intel
Pentium which is the only processor that
uses standard input/output the
programmer uses one load or ID install
st instruction to assess memory tanks
when the CPU is accused a load or store
instruction it will send the M R equal
signal through input on I n and outputs
or UT instruction is used to assess
input/output devices hence when a CPU is
accused and input or output is Russian
it's resent a io r eq signal now moving
through memory mod input/output in the
memory mapped i/o technique input/output
devices address and memory addresses
share the same address spaces in other
words there is no extra explicit signal
to indicate whether the requested
address is for a memory location or an
input/output device therefore when the
CPU sends out an address
there is no withdrawal by only looking
at all the signals from the CPU if the
address was for a memory location offer
and input output device but of course
there must be a witch to
difference just not by looking at the
signal from the CPU in general memory
mapped i/o is constructed using one
signal that is the mr EQ signal which is
used to signal both memory and
input/output device requests when the
CPU wants to access or read or write a
memory location or an input or two
device it always has set the M req
signal for example the M 60000 uses
memory mapped i/o and it can use the
move instruction to access the memory
and i/o device in memory mapped i/o the
address space of the system is
partitioned by the manufacturer that is
the range of address values into a set
of addresses for the memory and another
set for input/output devices after
examining the truth that is designed set
the manufacturer will construct
selection secretaries that implement the
partition for example using a 32-bit
addressing scheme a simple partition
scheme is described which have addresses
that starts with one referring to a
memory location and address the start
with 0 through F a and input/output
device then we can use the remaining 31
bits of the address as the actual
address portion for selecting a memory
location or input/output device that
brings us to the end of the section
thank you and see you in our next
section