CMOS SRAM Video Lecture - Electrical Engineering (EE)
FAQs on CMOS SRAM Video Lecture - Electrical Engineering (EE)
| 1. What is CMOS SRAM in electrical engineering? |  |
Ans. CMOS SRAM, or Complementary Metal-Oxide-Semiconductor Static Random-Access Memory, is a type of memory technology commonly used in digital integrated circuits. It is a volatile memory that stores data as long as power is supplied to the circuit. CMOS SRAM is known for its high-speed access and low power consumption characteristics, making it suitable for cache memory in microprocessors and other applications requiring fast and low-power data storage.
| 2. How does CMOS SRAM work? | |
Ans. CMOS SRAM is built using CMOS technology, which uses a combination of p-type and n-type metal-oxide-semiconductor field-effect transistors (MOSFETs). The memory cells in CMOS SRAM consist of six transistors arranged in a flip-flop configuration. These transistors enable the storage and retrieval of data in a static manner, without the need for refreshing like dynamic RAM (DRAM). When power is supplied, the stored data remains intact until it is overwritten or the power is turned off.
| 3. What are the advantages of CMOS SRAM over other memory technologies? | |
Ans. CMOS SRAM offers several advantages over other memory technologies. Firstly, it provides faster access times compared to dynamic RAM (DRAM) due to its static nature. This makes it suitable for high-speed cache memory in processors. Secondly, CMOS SRAM consumes relatively low power, making it efficient for battery-powered devices. Additionally, CMOS SRAM does not require refreshing, which simplifies its control circuitry. Lastly, CMOS SRAM has high immunity to noise and can operate at lower voltages, enhancing its reliability and performance.
| 4. What are the limitations of CMOS SRAM? | |
Ans. Despite its advantages, CMOS SRAM has certain limitations. One limitation is its relatively high cost compared to other memory technologies like DRAM or flash memory. This is because CMOS SRAM requires more transistors per bit of storage, resulting in higher manufacturing costs. Moreover, CMOS SRAM has limited density, meaning it cannot store as much data in the same physical space as other memory technologies. Lastly, CMOS SRAM is a volatile memory, meaning it loses data when power is removed, requiring data backup or constant power supply.
| 5. In what applications is CMOS SRAM commonly used? | |
Ans. CMOS SRAM finds application in various electronic devices and systems. It is commonly used as cache memory in microprocessors, where its fast access times and low power consumption are crucial for improving overall system performance. CMOS SRAM is also used in networking devices, such as routers and switches, for storing routing tables and temporary data. Additionally, it is utilized in graphics cards, embedded systems, and high-performance computing applications where fast and reliable data storage is required.
Text Transcript from Video
Oh
[Music]
ha ha ha
they just made all of us really
[Music]
[Music]
so we shall continue our discussion on
memories last class we introduced the
CMOS memory cell so continuing on that
so this CMOS memory would consist of the
address inputs here X decoder X you have
the driver you have the driver decoder
so these are the X address inputs and
from the output of the decoder you have
a number of lines okay so if you have
say eight address inputs here you will
have 2 to the power 8 lines so this
gives rise to 2 to the power 8 rows okay
so I am just drawing the two rows here
and then you have the different columns
okay this is one particular column where
you have the memory cell the memory cell
basically consists of in a CMOS case we
have seen it consists of 2 pass
transistors like this and 2 CMOS
inverters connected back to back okay
the toe CMOS inverter is connected back
to back so you have similar cells
along this okay and so this is one
column so you I am just showing two lows
similarly you have another other columns
okay so you have again just exactly same
similar cells okay
and here also okay now what is done is
when depending on the X address inputs
one of the out one of the output lines
of the decoder goes high and which
selects the pass transistors
corresponding to that particular row so
all the cells in that particular row are
selected so it lets one cell in each of
the columns one cell in each of those
columns is selected and that particular
cell is connected to the data line so
you have two lines actually one is
called the data and the other is the
data bar lines it is the curse of this
particular configuration here you have
an inverter so if one data one line is
high the other line will be low now the
next task is to select one of the one of
the columns so that is done again here
using fast transistors so you have the
i/o lines input/output lines so
so these pass transistors are connected
to these IO lines okay and this u this
input to these pass transistors comes
from the Y decoder Y decoder which
receives as input the Y address inputs
and the outputs are pass on to this
gates of these pass transistors so again
depending on the combination at the
input here okay one of the outputs only
one output of the Y decoder is going to
be high so it basically selects one
particular column so only the output of
one particular column is connected to
the i/o lines so depending on the input
address one row will be selected which
means that one particular cell in each
column is going to be selected so the
information available on the data lines
corresponds to that particular cell and
with the help of the Y decoder again we
are selecting one particular column so
the output of that particular column is
available on the i/o lines so depending
on the combination of the x and y inputs
one particular cell is selected so that
is how it works now you can you can
imagine that if we have a large size
memory okay say for example if you have
say 256 K memory bit memory that means J
will be 18 address lines so 9 X address
lines and y 9 while Y address lines and
there will be 2 to the power 9 rows and
2 to the power 9 columns okay so a 512
rows and 512 problems so these address
like this word lines and bit lines are
going to be extremely long and they have
large capacitances and resistances and
so there is going to be a lot of delay
in charging and discharging these lines
so let us take a particular example okay
I will just draw the particular cell in
the magnified form so the cell looks
like this you have the inverters here
the CMOS inverters this is one inverter
and you have this is another inverter
here okay and what what is done is this
in the cell the output of one inverter
is connected to the input of the other
so this is the cell so this is VDD this
is ground okay
you have the word lines running like
this so you have the pass transistors
which are activated by the word lines
and which connect the output of this
particular cell to the data line so this
is data lines say and this is the data
bar line okay now so you have the word
lines running all through the memory
array now this word line is connected to
the gate of the these pass transistors
and we know that in a MOS technology the
gates are usually made of poly silicon
so this word lines are usually run on
poly silicon so in fact I would better
draw it in this form okay to make it
clearer okay it is similar to drawing it
if this is the word line is the poly
silicon word line same then I shortened
so this is the poly silicon word line
and drawing it in red to distinguish and
this is the data line so the transistor
is formed at this thing so this is the
transistor and the gate is connected
here so this is the transistor
okay so basically what it does is when
this word line goes hi okay
this data line is connected to the
output of this cell so this word line
okay
runs all through the cell so it's a very
long word line okay and a large part of
the delay is due to the charging and
discharging of this data line so when
the output of the decoder changes then
this voltage on the data line should
change and so the entire if the the data
line the word line is a large
capacitance so the capacitance has to be
charged so let us take a small example
to see to find out the delays how to one
may calculate so let us assume take a
small problem okay small memory the 16 K
into 1 bit memory okay and so array is
128 cells into 128 cells array okay
array size
1 mm into 1 mm poly-silicon line which
is the word line 1 micron wide so that
is a 1 micron line okay
select transistors 1 micron that is the
size of the Select transistors channel
length of 1 micron and with the 1 micron
polysilicon sheet resistance is equal to
10 ohms per square capacitance
to substrate polylines for polyline
equal to 0.2 m20 farad per micron
squared and gate capacitance for femto
farad per micron squared so given these
details can we estimate the delay
required to charge the word lines okay
so that is a small problem let us see
how we are going to tackle it okay first
the polysilicon line this is a
polysilicon line we know the word line
is that details about this is given
polysilicon sheet resistance is equal to
10 ohms per square for those of you who
are not acquainted with this term of
sheet resistance see a resistance of any
line is given by resistivity the length
into the length divided by area now if
you have a line if you look at the top
top view of a line say this is the top
view okay this is the length of the line
okay and if this line has a width of W
okay and if this is made of a sheet of
material you know of thickness say T if
the if the material thickness is T so
suppose if you take the cross sectional
view okay this is L this is the
thickness
T
okay and this may be the weight W okay
so the resistance can be given as Rho L
divided by W into T okay now this is the
length this is the width of the line and
this is the thickness now if we assume a
square okay if you assume a square here
one square of this material then the
length is equal to the width if if you
take a one square of this material and
length is equal to weight this becomes
equal to Rho by T okay that is the
resistivity by thickness so if the
thickness of the material is constant
then we can define a resistance for a
square of the material the important
point to note here is that this
resistance of one square of the material
is independent of the size of the square
so if you take the same thickness of the
same material and you have a small
square or you have a large square okay
the resistance from one end of the this
line to the other it is the same
irrespective if you have a big square or
a small square so it does not depend on
the size of the square so in this case
the total resistance is now going to be
given by how many squares you have okay
if you know the sheet resistance which
is nothing but the resistance of one
square of that material okay
so the total resistance is going to be
the number of square since here you have
three squares so the resistance of this
particular line is going to be the
thrice the sheet resistance okay so that
is how we determine the resistance of a
line okay now here it is given that the
poly word line is one micron wide and
the array size is 1 mm into 1 mm so it
just runs for a length of 1 millimeter
and it is one micron wide so the number
of squares polyline number of squares is
one millimeter divided by one micron
which is 1000 so poly resistance
our se is equal to one millimeter by one
micron so that many squares you have the
length is one millimeter width is one
micron so a thousand squares into ten
ohms okay so the total resistance of the
polyline is ten kilo ohms okay now what
about the capacitance the total polyline
is again 1 millimeter why is 1
millimeter long but it runs partly if
you look at this figure this is the
polyline it is going to run partly on
the field oxide okay which is a thicker
oxide so it has a smaller capacitance
and that is given by the capacitance to
substrate of the polyline the
capacitance to substrate of the power to
substrate for the polyline is 0.2 femto
farad per micron squared okay so that is
the capacitance for this part of the
polyline okay whereas in where is it is
the runs over the when it is a part of
the mosfet okay you have the gate
capacitance okay which is higher because
the oxide thickness is less so partly
this polyline runs over thinner oxides
which forms the gate and partly over
thicker oxide for the remainder of the
line so if you have a 180 128 cell into
128 cell array there will be 256 such
transistors okay
to 256 such transistors because each
cell has got to select transistors so
and each transistor is 1 micron by 1
micron so the total capacitance is going
to be
poly capacitance say see is partly due
to the gate capacitance so the gate area
is the 256 transistors
okay so 256 into one micron into one
micron that is 256 micron squared into
for the gate capacitance is four femto
farad per centimeter square so 256 into
four so this is the total capacitance
due to gate plus so 256 micron for 256
micron it is running over gate oxide for
the remainder of one millimeter it is
going to run on field oxide so plus one
millimeter so that is 1000 micron minus
256 micron okay that is the field oxide
into one micron is the width okay so
this is the area into 0.2 femto farad
per micron squared so this is the total
capacitance okay so the total
capacitance is works out to one point
one seven four Pico farad okay so this
is the resistance and this is the
capacitance so the total rise time okay
estimated rise time if you have an RC
type of if you consider just RC type of
network is given by that is the time
required to rise up to ninety percent of
the final value is given by 2.3 RC so if
you take this R and C so this works out
to be 20 segment nanoseconds okay of
course this is a rather over estimate a
very large over estimate of the actual
delay because the the this considers R
and C separately
whereas this resistance and capacitance
is distributed throughout the line well
we if these are used as lump parameters
here but actual in actual practice they
are distributed
if you use a distributed parameters the
actual delay will be around 15
nanoseconds okay so if you use the
distributed parameters so this is much
less than this 27 nanoseconds so T if
you use distributed so this is T are for
lumped parameters so this will be around
15 minus and this is the actual value 15
nanoseconds this is gives a rough
estimate of the delay by assuming lumped
values of resistance and capacities one
resistance and one capacitance but in
since in actual practice the resistance
and capacitance are distributed one has
to do a distributed analysis using
distributed resistance and capacitance
where the delay if one does such an
analysis the delay would be
approximately 15 nanoseconds so this is
the order of delay of the of this word
line so this is an appreciable part of
the delay of a memory cell the time
required to access a particular memory
cell so obviously we have already
studied by CMOS drivers and we know that
by CMOS is capable of driving large
capacitances so instead of CMOS drivers
we shall be using by CMOS drivers that
we shall take it up when we when we look
at a bi CMOS memory our memories in the
next class may be okay now so this is
one aspect of the delay that is charging
or discharging the word line okay so we
require large we require devices okay
which are capable of our circuits
capable of charging or discharging large
capacitance capacitive loads okay to
drive this word lines now once we select
the particular cell okay so suppose this
particular cell is selected then
if when we are reading this cell reading
the information of the cell then the
information stored on this cell should
affect the data and the data bar lines
okay so that we get the information
regarding this cell on the data and data
bar lines and we are able to read the
information of this cell so this means
that this cell must be able to charge
and/or discharge this data and data bar
lines now these data and data bar lines
also represent large capacitive loads
because they are also running all along
the all along the memory array and these
lines will be as long as the word lines
so these data so these data and data bar
lines must also be charged
also constitute an important delay can
result in a large delay now the problem
here is that these data and data bar
lines must be charged or discharged with
the help of these transistors in the
memory cell now this since we know that
say for example if you have a 256 K
memory we have 256 K such cells and this
memory array takes up the major chunk of
the area of the total memory okay and so
these transistors in the memory cell
must be a small size transistors because
if we are going to make them big
transistors then the area of the cell
becomes very large okay so next this
transistors necessarily must be small
transistors because they take up a major
I mean if you just increase one
transistor to twice the size then the
whole memory size is going to go up by a
factor of two so one must at the same
time one must make it these transistors
small at the same time if you have small
transistors it is difficult to drive
these data lines okay using such small
transistors that is the problem okay
so how do we solve this problem okay
the way to solve it is to use what are
called sense amplifiers okay the sense
amplifiers will be used to actually
charge or discharge the data lines so
they are going to sense what is stored
in the memory okay
and based on that they are going to make
the one of the data lines go high and
the other data line go low so basically
the the charging and the discharging of
these large capacitive loads that is the
data lines are done by the sense
amplifiers and since we have we are
going to have only one sense amplifier
for example for one column okay so it
does not matter we can make them quite
large a transistors we can use quite
large transistors because the number of
sense amplifiers is going to be quite
small okay say for example if you have
again a 256 K kilo byte memory okay so
which means that two to the power 18
cells okay - 56,000 cells we have 2 to
the power nine columns so if we put one
sense amplifier per column we just have
512 sense amplifiers
okay so 512 compared to 256 thousand is
quite a small number so we can afford to
make this sense amplifiers quite large
and so that the data lines can be
charged and discharged at a faster rate
so what is done is now instead of
depending on the transistors in the cell
to charge or discharge the data lines we
will use sense amplifiers to do so and
these can be made quite large so what we
have is we have here a sense amplifier
okay for each column we have a sense
amplifier connected to the data lines
okay now what is this sense amplifier
let us see okay
and the sense amplifier is also nothing
but two inverters connected back to back
okay so just draw it in a magnified form
so this is suppose this is the data
lines on which the cells are here okay
so the sense amplifier consists of again
two CMOS inverters okay so this is one
inverter this is another inverter and
the output of one inverter goes to the
input of the other as usual okay and
this these are connected to the data
lines this is goes to VDD and the source
goes to an input here which is the sense
input okay and this goes to ground okay
so this is the sense amplifier now this
is nothing but two inverters back to
back now if you have such a structure
okay basically two inverters connected
back to back okay if like this so this
is one inverter and this is another
inverter and this is connected to two
lines so you can have two possible
combinations okay that is either this is
one and this is zero okay so this goes
to one this will go to 0 and this 0 1 or
you can have the other combination this
is 0 and this is 1 okay there are two
possible combinations in which which are
stable ok now so if you have such a
combination it will always tend to go to
one of these two possible combinations
and and there is a large positive
feedback involved so if it is in the if
it is maintained in unsteady unstable
condition it will always tend to go to
one of the two stage
which is favored okay now what happens
is if you consider this okay if we
maintain these two put the data and data
bar lines at the same voltage okay data
and data bar lines are the same voltage
and then if by some mechanism or some
reason one of the voltages are changed
by a small amount okay so suppose this
is V and this is V Plus Delta V okay so
this voltage is higher compared to this
then and if we then turn on this sense
amplifier
since this voltage is higher so this
will always tend to go to the higher
value that is VDD and this one will go
to ground so this one will go to logic
one and this one will go to zero on the
other hand if this is V and this is V
minus Delta V that is this has the lower
voltage here okay so what will happen is
this will tend to go to this side will
tend to go to zero whereas on the other
side which is a higher voltage will tend
to go to one so because of the large
feedback positive feedback here in this
circuit okay any discrepancy here in
between the two voltages is going to be
magnified and is or amplified and so one
line will go to zero and the other line
will go to one and this configuration
will go to one of its two possible
steady states so this sense amplifier is
included in this cell here the other
thing which is done is so what we must
do is we must initially have equal
voltages on these lines okay so what we
do is we do a pre charging so both these
lines the data and data bar lines are
maintained in the pre charge condition
so what we have is here
a pre-charge circuit okay which is
nothing but two transistors here okay
say these are two P MOS transistors okay
and here you have a voltage VP which is
the pre-charge voltage and this is the
pre-charge line so again it is a
two-phase clock who is used so when the
pre-charge volt pre-chat input here goes
low okay when the pre-charge input here
goes low these two p MOS transistors
they turn on okay and this breach our
voltage here which is available here is
now available in the data and data bar
lines so the data and data bar lines are
both pre charged to this initial value
VP ok pre charge voltage okay so in this
pre child value is input is low then
both the data and data bar lines have
the same values now when we select a
particular cell the word line goes high
particular cell is selected now when a
particular cell is selected okay what
happens is as we said it can be in one
of the two possible combinations okay
that is either if you look at the cell
alright which is nothing but again two
inverters connected back to back so if
this is a cell here okay so if there can
be only two possible combinations in one
combination if this is logic say zero
and this is one okay then it means that
this transistor is on n Mo's transistor
is on and this is off and here this is
one it means this is on P MOS is on this
is off so this is one particular
combination so if this is the particular
combination what is going to happen is
this line because the N Mo's transistor
is on tends to get discharged through
the on transistor so this voltage here
on this line is going to tend to get
reduced whereas the
line this P mas is on so there is going
to be a charging current and this
voltage okay this data line here tends
to go in tends to get charged up okay so
if this is the condition of the cell
okay
then what is going to happen is one line
is going to be pulled down okay and the
other line is going to be pulled up so
there is going to be a small difference
okay
in the voltages between the data and
data bar lines so suppose the data and
data bar lines charge to VP okay and
then one line will go above VP this way
go below VP this side and this one will
go above B if the state of the cell was
different okay
then it would be in the different
direction okay so depending on the state
of the cell okay
voltage difference is created now then
what happens is the sense amplifier okay
the sense amplifier is turned on once
the cell once the difference in the
voltage a small difference in voltage C
because the cell is uses small
transistors so it will take a long time
for any large appreciable voltage
difference between the lines to develop
so when a small difference in voltage is
develops a 0.1 volt or so the sense
amplifier is turned on okay so this is
the sense amplifier okay so when this
transistor is turned on okay this sense
amplifier is activated if this is off
the sense amplifier is off so when this
sense amplifier is activated okay when
this sense amplifier is activated what
happens is this is again going to go to
one of the two states so when if there
is a small difference initial difference
say this is beep V P plus Delta V and if
this is V P minus Delta V okay so this
voltage being larger than this voltage
VP plus Delta V being larger than V P
minus Delta V here so there will be a
tendency for this voltage to go up to
VDD that is their high voltage and
this voltage to go down to ground okay
so depending on the initial state of the
data and data bar lines seen by the
sense amplifier okay one line is going
to go high and the other line is going
to go low so depending on the
information stored in the cell okay one
line is going to go high and one line is
going to go low so that is how the sense
amplifier is used to speed up the
operation of the charging and since this
is a big transistor this can these are
big transistors they can charge or
discharge the data lines faster compared
to the small transistor so basically
again just to go through the operation
of this memory okay so what is done when
you are reading okay X address and a Y
address depending on the X address and
the Y address a particular row is
selected okay and a particular column is
selected so when a particular row is
selected the cell is connected to the
data lines okay and this is going to
change the this depending on the
configuration or the status of the
individual transistors in this in this
cell okay
the the data and data bar line is data
but voltages are going to change the
data and data but voltages are kept at a
pre-charged value they are equated
initially okay so one line is going to
go up well small amount and the other
line is going to go down by a small
amount
this is then once a small difference is
created a sense amplifier is turned on
it is important that the sense amplifier
is not turned on right away because what
happens is if the sense amplifier is
kept on initially then what happens is
due to small some noise voltages the
sense amplifier may tend to go in in one
of the two directions okay making the
data line go to one of the tools
high or low directions so once the small
difference in voltage is created due to
the the cell voltage the configure the
condition of the transistors in the cell
then the sense amplifier is turned on
which makes the data one of the data
lines go high and the other one go low
and then one of the columns so this
happens in all the columns because one
cell is selected in all the columns now
due to this configuration here due to
the presence of these pass transistors
okay and the Y decoder selects only one
of the columns okay one of the column is
selected which is connected to the input
output lines and the information on that
particular column only
is passed on to the i/o lines okay so
for writing mechanism okay what is done
is this i/o lines can be used to write
information into the cells by forcing
voltages on these data lines so if one
line is made to go high and the other
line is made to go low then you
basically can write into these
particular into a particular cell okay
so
so this is how a CMOS memory cell is
going to work okay now we shall see that
the CMOS okay we have already seen that
the BI CMOS okay has certain advantages
over CMOS okay and this is especially in
this in the areas of driving large
capacitive loads and here we have seen
that expect we have seen in as an
example that the word line has a large
capacitance and so for example a bi CMOS
can be used to drive this large word
lines so in fact the bi CMOS can be used
in a number of areas in this memory in
the static Ram cell which we have
discussed okay now
so in fact bi CMOS memories have become
quite popular and they have much
improved performance when compared to
the CMOS memory okay now we shall take
up the case of bi CMOS static Ram and
see the particular areas okay where you
introduce bipolar transistors the
particular to speed up the operation of
the particular static Ram okay
now it is not that in a when you have bi
CMOS technology available you would
introduce bipolar transistors into all
areas of the static Ram okay you we will
introduce you will have to introduce
this bipolar transistors judiciously in
certain areas now if you just look at
the block diagram of the static Ram you
have the X address inputs the driver
decoder then you have the memory array
memory cell array
okay and then you have the sense
amplifiers okay and then you have the Y
decoder and
okay now so these are the Y inputs here
so in fact you have in bi CMOS usually
the interface circuits are the bipolar
circuit so you have buffers here to
convert the voltage levels from the from
the for example if you are using a ECL
interface from ECL to CMOS so you have a
y-buffer and you will also have an X
buffer here okay so I will put X decoder
driver Y decoder driver and you have X
buffer okay so this is the block diagram
of the memory array okay now let us see
which areas we would use also you have
some control circuitry yes we have some
control circuitry here okay which
actually is required to choose whether
you want to do a read operation or a
write operation and then you have the
outputs coming from this okay so you
will have output buffers okay okay now
so this is the this control this is
going to okay now for this which
technology would be used in which
regions for example if you take the
memory cell array
okay now this memory cell array
constitutes the major portion of the
device of the cell okay in terms of area
so this has to be in a technology which
consume less area also since the maximum
number of transistors okay are in this
memory cell array the power dissipation
that total power dissipation of the cell
is going to depend on the power
dissipation of the memory cell array so
this cell okay has to be made in using
such a technology which has low power
dissipation and has less area takes up
less area so this memory cell array is
is basically done using CMOS okay so
this the memory cell array will remain
CMOS in spy CMOS in memory okay so I
just
this is CMOS okay so the memory cell
array in even in a bi CMOS is going to
be a CMOS so we do not introduce bipolar
transistors in the memory cell array
because the bipolar cell a bipolar takes
up a lot of area and also a large power
the power dissipation is going to go up
okay so what we are designing is for a
large memory okay so this would still be
a CMOS okay we know that in ECL for
example if this were made of ECL then
the power dissipation would be quite
exotic white a lot and so we cannot
afford this in a large memory now what
about this decoder drivers this decoder
drivers would be using by CMOS okay
because these have to drive very large
capacitances and we have already seen
that this by CMOS is capable of very
large driving large capacitance okay so
we make this Y decoder driver also using
bi CMOS so this is the symbol for bi
CMOS that is we basically use bi CMOS
gates okay to drive these large
capacitances so this will be the decoder
driver will be driving the large
capacity the word-line capacitances and
also the Y decoder driver has to drive
large capacitances so this are basically
the bi CMOS the sense amplification in
this case the sense amplifier usually in
a bi CMOS memory is done using bipolar
transistors why because bipolar
transistors we have already
scene has a very large transconductance
much larger compared to the CMOS
counterparts and that is used to sense
this use for sensing in this memory now
a small voltage okay a small voltage can
be sensed much much easily okay much
more easily using bipolar transistors
okay a small difference of less than 100
millivolts can be sensed by bipolar
transistors which will result in a large
change in current which is not true in
the case of MOS transistors because you
require a large difference much larger
difference in the gate voltage to be
really sensed because of the large
strands larger this is because of the
larger transconductance in bipolar
transistor so bipolar transistors are
generally used in this sense amplifier
so this is completely bipolar
okay so just keep this bipolar so this
blocks like this this is a bipolar now
the control again has a combination of
bipolar and CMOS so this in the bi CMOS
whereas this outputs buffers in general
because these are supposed to be high
speed circuits okay many of these bi
CMOS memories use the ECL logic levels
okay the input and output levels are ECL
so you require buffers to convert this
levels into the standard CMOS levels
because you see the memory cell array is
actually using CMOS so what is done is
it has to be converted to CMOS levels so
in fact here you have negative voltages
okay ECL level is negative voltage if
you are using an ECL level okay and this
has to be converted and this has to work
in a CMOS environment inside okay
so what is done is you have negative
voltages but it is still in a CMOS a
type of level
that is suppose you want five volt
memory okay so this is converted into
same in a bi CMOS you know that it out
put is going to go to be VDD minus vbe2
VB which is the lower level so if zero
is going to be VDD okay you can
represent zero voltage is VDD and - you
have minus VSS so in fact the voltage
levels internal to the circuit can be
minus 0.62 minus say four point four
okay so this is minus point six is
considered logic high and well as minus
four point four is considered logic low
so basically it the CMOS is going to
operate in the same way it is just a
level shifting down to a negative
voltages okay so in in this case the
memory okay so you have the full swing
if you have five volt you have a 5 volt
full swing for this operation of the
memory cell array so only the voltage
levels would be negative instead of
positive okay so zero volt would be high
and minus 5 volt would be low okay so
what we shall do in the next class is we
shall study in detail by CMOS static Ram
okay and see how it is realized in in
the how attic Ram can be realized or is
realized in the BI CMOS environment
[Music]
[Music]
Oh
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you
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ha ha ha
they just made all of us really
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[Music]
so we shall continue our discussion on
memories last class we introduced the
CMOS memory cell so continuing on that
so this CMOS memory would consist of the
address inputs here X decoder X you have
the driver you have the driver decoder
so these are the X address inputs and
from the output of the decoder you have
a number of lines okay so if you have
say eight address inputs here you will
have 2 to the power 8 lines so this
gives rise to 2 to the power 8 rows okay
so I am just drawing the two rows here
and then you have the different columns
okay this is one particular column where
you have the memory cell the memory cell
basically consists of in a CMOS case we
have seen it consists of 2 pass
transistors like this and 2 CMOS
inverters connected back to back okay
the toe CMOS inverter is connected back
to back so you have similar cells
along this okay and so this is one
column so you I am just showing two lows
similarly you have another other columns
okay so you have again just exactly same
similar cells okay
and here also okay now what is done is
when depending on the X address inputs
one of the out one of the output lines
of the decoder goes high and which
selects the pass transistors
corresponding to that particular row so
all the cells in that particular row are
selected so it lets one cell in each of
the columns one cell in each of those
columns is selected and that particular
cell is connected to the data line so
you have two lines actually one is
called the data and the other is the
data bar lines it is the curse of this
particular configuration here you have
an inverter so if one data one line is
high the other line will be low now the
next task is to select one of the one of
the columns so that is done again here
using fast transistors so you have the
i/o lines input/output lines so
so these pass transistors are connected
to these IO lines okay and this u this
input to these pass transistors comes
from the Y decoder Y decoder which
receives as input the Y address inputs
and the outputs are pass on to this
gates of these pass transistors so again
depending on the combination at the
input here okay one of the outputs only
one output of the Y decoder is going to
be high so it basically selects one
particular column so only the output of
one particular column is connected to
the i/o lines so depending on the input
address one row will be selected which
means that one particular cell in each
column is going to be selected so the
information available on the data lines
corresponds to that particular cell and
with the help of the Y decoder again we
are selecting one particular column so
the output of that particular column is
available on the i/o lines so depending
on the combination of the x and y inputs
one particular cell is selected so that
is how it works now you can you can
imagine that if we have a large size
memory okay say for example if you have
say 256 K memory bit memory that means J
will be 18 address lines so 9 X address
lines and y 9 while Y address lines and
there will be 2 to the power 9 rows and
2 to the power 9 columns okay so a 512
rows and 512 problems so these address
like this word lines and bit lines are
going to be extremely long and they have
large capacitances and resistances and
so there is going to be a lot of delay
in charging and discharging these lines
so let us take a particular example okay
I will just draw the particular cell in
the magnified form so the cell looks
like this you have the inverters here
the CMOS inverters this is one inverter
and you have this is another inverter
here okay and what what is done is this
in the cell the output of one inverter
is connected to the input of the other
so this is the cell so this is VDD this
is ground okay
you have the word lines running like
this so you have the pass transistors
which are activated by the word lines
and which connect the output of this
particular cell to the data line so this
is data lines say and this is the data
bar line okay now so you have the word
lines running all through the memory
array now this word line is connected to
the gate of the these pass transistors
and we know that in a MOS technology the
gates are usually made of poly silicon
so this word lines are usually run on
poly silicon so in fact I would better
draw it in this form okay to make it
clearer okay it is similar to drawing it
if this is the word line is the poly
silicon word line same then I shortened
so this is the poly silicon word line
and drawing it in red to distinguish and
this is the data line so the transistor
is formed at this thing so this is the
transistor and the gate is connected
here so this is the transistor
okay so basically what it does is when
this word line goes hi okay
this data line is connected to the
output of this cell so this word line
okay
runs all through the cell so it's a very
long word line okay and a large part of
the delay is due to the charging and
discharging of this data line so when
the output of the decoder changes then
this voltage on the data line should
change and so the entire if the the data
line the word line is a large
capacitance so the capacitance has to be
charged so let us take a small example
to see to find out the delays how to one
may calculate so let us assume take a
small problem okay small memory the 16 K
into 1 bit memory okay and so array is
128 cells into 128 cells array okay
array size
1 mm into 1 mm poly-silicon line which
is the word line 1 micron wide so that
is a 1 micron line okay
select transistors 1 micron that is the
size of the Select transistors channel
length of 1 micron and with the 1 micron
polysilicon sheet resistance is equal to
10 ohms per square capacitance
to substrate polylines for polyline
equal to 0.2 m20 farad per micron
squared and gate capacitance for femto
farad per micron squared so given these
details can we estimate the delay
required to charge the word lines okay
so that is a small problem let us see
how we are going to tackle it okay first
the polysilicon line this is a
polysilicon line we know the word line
is that details about this is given
polysilicon sheet resistance is equal to
10 ohms per square for those of you who
are not acquainted with this term of
sheet resistance see a resistance of any
line is given by resistivity the length
into the length divided by area now if
you have a line if you look at the top
top view of a line say this is the top
view okay this is the length of the line
okay and if this line has a width of W
okay and if this is made of a sheet of
material you know of thickness say T if
the if the material thickness is T so
suppose if you take the cross sectional
view okay this is L this is the
thickness
T
okay and this may be the weight W okay
so the resistance can be given as Rho L
divided by W into T okay now this is the
length this is the width of the line and
this is the thickness now if we assume a
square okay if you assume a square here
one square of this material then the
length is equal to the width if if you
take a one square of this material and
length is equal to weight this becomes
equal to Rho by T okay that is the
resistivity by thickness so if the
thickness of the material is constant
then we can define a resistance for a
square of the material the important
point to note here is that this
resistance of one square of the material
is independent of the size of the square
so if you take the same thickness of the
same material and you have a small
square or you have a large square okay
the resistance from one end of the this
line to the other it is the same
irrespective if you have a big square or
a small square so it does not depend on
the size of the square so in this case
the total resistance is now going to be
given by how many squares you have okay
if you know the sheet resistance which
is nothing but the resistance of one
square of that material okay
so the total resistance is going to be
the number of square since here you have
three squares so the resistance of this
particular line is going to be the
thrice the sheet resistance okay so that
is how we determine the resistance of a
line okay now here it is given that the
poly word line is one micron wide and
the array size is 1 mm into 1 mm so it
just runs for a length of 1 millimeter
and it is one micron wide so the number
of squares polyline number of squares is
one millimeter divided by one micron
which is 1000 so poly resistance
our se is equal to one millimeter by one
micron so that many squares you have the
length is one millimeter width is one
micron so a thousand squares into ten
ohms okay so the total resistance of the
polyline is ten kilo ohms okay now what
about the capacitance the total polyline
is again 1 millimeter why is 1
millimeter long but it runs partly if
you look at this figure this is the
polyline it is going to run partly on
the field oxide okay which is a thicker
oxide so it has a smaller capacitance
and that is given by the capacitance to
substrate of the polyline the
capacitance to substrate of the power to
substrate for the polyline is 0.2 femto
farad per micron squared okay so that is
the capacitance for this part of the
polyline okay whereas in where is it is
the runs over the when it is a part of
the mosfet okay you have the gate
capacitance okay which is higher because
the oxide thickness is less so partly
this polyline runs over thinner oxides
which forms the gate and partly over
thicker oxide for the remainder of the
line so if you have a 180 128 cell into
128 cell array there will be 256 such
transistors okay
to 256 such transistors because each
cell has got to select transistors so
and each transistor is 1 micron by 1
micron so the total capacitance is going
to be
poly capacitance say see is partly due
to the gate capacitance so the gate area
is the 256 transistors
okay so 256 into one micron into one
micron that is 256 micron squared into
for the gate capacitance is four femto
farad per centimeter square so 256 into
four so this is the total capacitance
due to gate plus so 256 micron for 256
micron it is running over gate oxide for
the remainder of one millimeter it is
going to run on field oxide so plus one
millimeter so that is 1000 micron minus
256 micron okay that is the field oxide
into one micron is the width okay so
this is the area into 0.2 femto farad
per micron squared so this is the total
capacitance okay so the total
capacitance is works out to one point
one seven four Pico farad okay so this
is the resistance and this is the
capacitance so the total rise time okay
estimated rise time if you have an RC
type of if you consider just RC type of
network is given by that is the time
required to rise up to ninety percent of
the final value is given by 2.3 RC so if
you take this R and C so this works out
to be 20 segment nanoseconds okay of
course this is a rather over estimate a
very large over estimate of the actual
delay because the the this considers R
and C separately
whereas this resistance and capacitance
is distributed throughout the line well
we if these are used as lump parameters
here but actual in actual practice they
are distributed
if you use a distributed parameters the
actual delay will be around 15
nanoseconds okay so if you use the
distributed parameters so this is much
less than this 27 nanoseconds so T if
you use distributed so this is T are for
lumped parameters so this will be around
15 minus and this is the actual value 15
nanoseconds this is gives a rough
estimate of the delay by assuming lumped
values of resistance and capacities one
resistance and one capacitance but in
since in actual practice the resistance
and capacitance are distributed one has
to do a distributed analysis using
distributed resistance and capacitance
where the delay if one does such an
analysis the delay would be
approximately 15 nanoseconds so this is
the order of delay of the of this word
line so this is an appreciable part of
the delay of a memory cell the time
required to access a particular memory
cell so obviously we have already
studied by CMOS drivers and we know that
by CMOS is capable of driving large
capacitances so instead of CMOS drivers
we shall be using by CMOS drivers that
we shall take it up when we when we look
at a bi CMOS memory our memories in the
next class may be okay now so this is
one aspect of the delay that is charging
or discharging the word line okay so we
require large we require devices okay
which are capable of our circuits
capable of charging or discharging large
capacitance capacitive loads okay to
drive this word lines now once we select
the particular cell okay so suppose this
particular cell is selected then
if when we are reading this cell reading
the information of the cell then the
information stored on this cell should
affect the data and the data bar lines
okay so that we get the information
regarding this cell on the data and data
bar lines and we are able to read the
information of this cell so this means
that this cell must be able to charge
and/or discharge this data and data bar
lines now these data and data bar lines
also represent large capacitive loads
because they are also running all along
the all along the memory array and these
lines will be as long as the word lines
so these data so these data and data bar
lines must also be charged
also constitute an important delay can
result in a large delay now the problem
here is that these data and data bar
lines must be charged or discharged with
the help of these transistors in the
memory cell now this since we know that
say for example if you have a 256 K
memory we have 256 K such cells and this
memory array takes up the major chunk of
the area of the total memory okay and so
these transistors in the memory cell
must be a small size transistors because
if we are going to make them big
transistors then the area of the cell
becomes very large okay so next this
transistors necessarily must be small
transistors because they take up a major
I mean if you just increase one
transistor to twice the size then the
whole memory size is going to go up by a
factor of two so one must at the same
time one must make it these transistors
small at the same time if you have small
transistors it is difficult to drive
these data lines okay using such small
transistors that is the problem okay
so how do we solve this problem okay
the way to solve it is to use what are
called sense amplifiers okay the sense
amplifiers will be used to actually
charge or discharge the data lines so
they are going to sense what is stored
in the memory okay
and based on that they are going to make
the one of the data lines go high and
the other data line go low so basically
the the charging and the discharging of
these large capacitive loads that is the
data lines are done by the sense
amplifiers and since we have we are
going to have only one sense amplifier
for example for one column okay so it
does not matter we can make them quite
large a transistors we can use quite
large transistors because the number of
sense amplifiers is going to be quite
small okay say for example if you have
again a 256 K kilo byte memory okay so
which means that two to the power 18
cells okay - 56,000 cells we have 2 to
the power nine columns so if we put one
sense amplifier per column we just have
512 sense amplifiers
okay so 512 compared to 256 thousand is
quite a small number so we can afford to
make this sense amplifiers quite large
and so that the data lines can be
charged and discharged at a faster rate
so what is done is now instead of
depending on the transistors in the cell
to charge or discharge the data lines we
will use sense amplifiers to do so and
these can be made quite large so what we
have is we have here a sense amplifier
okay for each column we have a sense
amplifier connected to the data lines
okay now what is this sense amplifier
let us see okay
and the sense amplifier is also nothing
but two inverters connected back to back
okay so just draw it in a magnified form
so this is suppose this is the data
lines on which the cells are here okay
so the sense amplifier consists of again
two CMOS inverters okay so this is one
inverter this is another inverter and
the output of one inverter goes to the
input of the other as usual okay and
this these are connected to the data
lines this is goes to VDD and the source
goes to an input here which is the sense
input okay and this goes to ground okay
so this is the sense amplifier now this
is nothing but two inverters back to
back now if you have such a structure
okay basically two inverters connected
back to back okay if like this so this
is one inverter and this is another
inverter and this is connected to two
lines so you can have two possible
combinations okay that is either this is
one and this is zero okay so this goes
to one this will go to 0 and this 0 1 or
you can have the other combination this
is 0 and this is 1 okay there are two
possible combinations in which which are
stable ok now so if you have such a
combination it will always tend to go to
one of these two possible combinations
and and there is a large positive
feedback involved so if it is in the if
it is maintained in unsteady unstable
condition it will always tend to go to
one of the two stage
which is favored okay now what happens
is if you consider this okay if we
maintain these two put the data and data
bar lines at the same voltage okay data
and data bar lines are the same voltage
and then if by some mechanism or some
reason one of the voltages are changed
by a small amount okay so suppose this
is V and this is V Plus Delta V okay so
this voltage is higher compared to this
then and if we then turn on this sense
amplifier
since this voltage is higher so this
will always tend to go to the higher
value that is VDD and this one will go
to ground so this one will go to logic
one and this one will go to zero on the
other hand if this is V and this is V
minus Delta V that is this has the lower
voltage here okay so what will happen is
this will tend to go to this side will
tend to go to zero whereas on the other
side which is a higher voltage will tend
to go to one so because of the large
feedback positive feedback here in this
circuit okay any discrepancy here in
between the two voltages is going to be
magnified and is or amplified and so one
line will go to zero and the other line
will go to one and this configuration
will go to one of its two possible
steady states so this sense amplifier is
included in this cell here the other
thing which is done is so what we must
do is we must initially have equal
voltages on these lines okay so what we
do is we do a pre charging so both these
lines the data and data bar lines are
maintained in the pre charge condition
so what we have is here
a pre-charge circuit okay which is
nothing but two transistors here okay
say these are two P MOS transistors okay
and here you have a voltage VP which is
the pre-charge voltage and this is the
pre-charge line so again it is a
two-phase clock who is used so when the
pre-charge volt pre-chat input here goes
low okay when the pre-charge input here
goes low these two p MOS transistors
they turn on okay and this breach our
voltage here which is available here is
now available in the data and data bar
lines so the data and data bar lines are
both pre charged to this initial value
VP ok pre charge voltage okay so in this
pre child value is input is low then
both the data and data bar lines have
the same values now when we select a
particular cell the word line goes high
particular cell is selected now when a
particular cell is selected okay what
happens is as we said it can be in one
of the two possible combinations okay
that is either if you look at the cell
alright which is nothing but again two
inverters connected back to back so if
this is a cell here okay so if there can
be only two possible combinations in one
combination if this is logic say zero
and this is one okay then it means that
this transistor is on n Mo's transistor
is on and this is off and here this is
one it means this is on P MOS is on this
is off so this is one particular
combination so if this is the particular
combination what is going to happen is
this line because the N Mo's transistor
is on tends to get discharged through
the on transistor so this voltage here
on this line is going to tend to get
reduced whereas the
line this P mas is on so there is going
to be a charging current and this
voltage okay this data line here tends
to go in tends to get charged up okay so
if this is the condition of the cell
okay
then what is going to happen is one line
is going to be pulled down okay and the
other line is going to be pulled up so
there is going to be a small difference
okay
in the voltages between the data and
data bar lines so suppose the data and
data bar lines charge to VP okay and
then one line will go above VP this way
go below VP this side and this one will
go above B if the state of the cell was
different okay
then it would be in the different
direction okay so depending on the state
of the cell okay
voltage difference is created now then
what happens is the sense amplifier okay
the sense amplifier is turned on once
the cell once the difference in the
voltage a small difference in voltage C
because the cell is uses small
transistors so it will take a long time
for any large appreciable voltage
difference between the lines to develop
so when a small difference in voltage is
develops a 0.1 volt or so the sense
amplifier is turned on okay so this is
the sense amplifier okay so when this
transistor is turned on okay this sense
amplifier is activated if this is off
the sense amplifier is off so when this
sense amplifier is activated okay when
this sense amplifier is activated what
happens is this is again going to go to
one of the two states so when if there
is a small difference initial difference
say this is beep V P plus Delta V and if
this is V P minus Delta V okay so this
voltage being larger than this voltage
VP plus Delta V being larger than V P
minus Delta V here so there will be a
tendency for this voltage to go up to
VDD that is their high voltage and
this voltage to go down to ground okay
so depending on the initial state of the
data and data bar lines seen by the
sense amplifier okay one line is going
to go high and the other line is going
to go low so depending on the
information stored in the cell okay one
line is going to go high and one line is
going to go low so that is how the sense
amplifier is used to speed up the
operation of the charging and since this
is a big transistor this can these are
big transistors they can charge or
discharge the data lines faster compared
to the small transistor so basically
again just to go through the operation
of this memory okay so what is done when
you are reading okay X address and a Y
address depending on the X address and
the Y address a particular row is
selected okay and a particular column is
selected so when a particular row is
selected the cell is connected to the
data lines okay and this is going to
change the this depending on the
configuration or the status of the
individual transistors in this in this
cell okay
the the data and data bar line is data
but voltages are going to change the
data and data but voltages are kept at a
pre-charged value they are equated
initially okay so one line is going to
go up well small amount and the other
line is going to go down by a small
amount
this is then once a small difference is
created a sense amplifier is turned on
it is important that the sense amplifier
is not turned on right away because what
happens is if the sense amplifier is
kept on initially then what happens is
due to small some noise voltages the
sense amplifier may tend to go in in one
of the two directions okay making the
data line go to one of the tools
high or low directions so once the small
difference in voltage is created due to
the the cell voltage the configure the
condition of the transistors in the cell
then the sense amplifier is turned on
which makes the data one of the data
lines go high and the other one go low
and then one of the columns so this
happens in all the columns because one
cell is selected in all the columns now
due to this configuration here due to
the presence of these pass transistors
okay and the Y decoder selects only one
of the columns okay one of the column is
selected which is connected to the input
output lines and the information on that
particular column only
is passed on to the i/o lines okay so
for writing mechanism okay what is done
is this i/o lines can be used to write
information into the cells by forcing
voltages on these data lines so if one
line is made to go high and the other
line is made to go low then you
basically can write into these
particular into a particular cell okay
so
so this is how a CMOS memory cell is
going to work okay now we shall see that
the CMOS okay we have already seen that
the BI CMOS okay has certain advantages
over CMOS okay and this is especially in
this in the areas of driving large
capacitive loads and here we have seen
that expect we have seen in as an
example that the word line has a large
capacitance and so for example a bi CMOS
can be used to drive this large word
lines so in fact the bi CMOS can be used
in a number of areas in this memory in
the static Ram cell which we have
discussed okay now
so in fact bi CMOS memories have become
quite popular and they have much
improved performance when compared to
the CMOS memory okay now we shall take
up the case of bi CMOS static Ram and
see the particular areas okay where you
introduce bipolar transistors the
particular to speed up the operation of
the particular static Ram okay
now it is not that in a when you have bi
CMOS technology available you would
introduce bipolar transistors into all
areas of the static Ram okay you we will
introduce you will have to introduce
this bipolar transistors judiciously in
certain areas now if you just look at
the block diagram of the static Ram you
have the X address inputs the driver
decoder then you have the memory array
memory cell array
okay and then you have the sense
amplifiers okay and then you have the Y
decoder and
okay now so these are the Y inputs here
so in fact you have in bi CMOS usually
the interface circuits are the bipolar
circuit so you have buffers here to
convert the voltage levels from the from
the for example if you are using a ECL
interface from ECL to CMOS so you have a
y-buffer and you will also have an X
buffer here okay so I will put X decoder
driver Y decoder driver and you have X
buffer okay so this is the block diagram
of the memory array okay now let us see
which areas we would use also you have
some control circuitry yes we have some
control circuitry here okay which
actually is required to choose whether
you want to do a read operation or a
write operation and then you have the
outputs coming from this okay so you
will have output buffers okay okay now
so this is the this control this is
going to okay now for this which
technology would be used in which
regions for example if you take the
memory cell array
okay now this memory cell array
constitutes the major portion of the
device of the cell okay in terms of area
so this has to be in a technology which
consume less area also since the maximum
number of transistors okay are in this
memory cell array the power dissipation
that total power dissipation of the cell
is going to depend on the power
dissipation of the memory cell array so
this cell okay has to be made in using
such a technology which has low power
dissipation and has less area takes up
less area so this memory cell array is
is basically done using CMOS okay so
this the memory cell array will remain
CMOS in spy CMOS in memory okay so I
just
this is CMOS okay so the memory cell
array in even in a bi CMOS is going to
be a CMOS so we do not introduce bipolar
transistors in the memory cell array
because the bipolar cell a bipolar takes
up a lot of area and also a large power
the power dissipation is going to go up
okay so what we are designing is for a
large memory okay so this would still be
a CMOS okay we know that in ECL for
example if this were made of ECL then
the power dissipation would be quite
exotic white a lot and so we cannot
afford this in a large memory now what
about this decoder drivers this decoder
drivers would be using by CMOS okay
because these have to drive very large
capacitances and we have already seen
that this by CMOS is capable of very
large driving large capacitance okay so
we make this Y decoder driver also using
bi CMOS so this is the symbol for bi
CMOS that is we basically use bi CMOS
gates okay to drive these large
capacitances so this will be the decoder
driver will be driving the large
capacity the word-line capacitances and
also the Y decoder driver has to drive
large capacitances so this are basically
the bi CMOS the sense amplification in
this case the sense amplifier usually in
a bi CMOS memory is done using bipolar
transistors why because bipolar
transistors we have already
scene has a very large transconductance
much larger compared to the CMOS
counterparts and that is used to sense
this use for sensing in this memory now
a small voltage okay a small voltage can
be sensed much much easily okay much
more easily using bipolar transistors
okay a small difference of less than 100
millivolts can be sensed by bipolar
transistors which will result in a large
change in current which is not true in
the case of MOS transistors because you
require a large difference much larger
difference in the gate voltage to be
really sensed because of the large
strands larger this is because of the
larger transconductance in bipolar
transistor so bipolar transistors are
generally used in this sense amplifier
so this is completely bipolar
okay so just keep this bipolar so this
blocks like this this is a bipolar now
the control again has a combination of
bipolar and CMOS so this in the bi CMOS
whereas this outputs buffers in general
because these are supposed to be high
speed circuits okay many of these bi
CMOS memories use the ECL logic levels
okay the input and output levels are ECL
so you require buffers to convert this
levels into the standard CMOS levels
because you see the memory cell array is
actually using CMOS so what is done is
it has to be converted to CMOS levels so
in fact here you have negative voltages
okay ECL level is negative voltage if
you are using an ECL level okay and this
has to be converted and this has to work
in a CMOS environment inside okay
so what is done is you have negative
voltages but it is still in a CMOS a
type of level
that is suppose you want five volt
memory okay so this is converted into
same in a bi CMOS you know that it out
put is going to go to be VDD minus vbe2
VB which is the lower level so if zero
is going to be VDD okay you can
represent zero voltage is VDD and - you
have minus VSS so in fact the voltage
levels internal to the circuit can be
minus 0.62 minus say four point four
okay so this is minus point six is
considered logic high and well as minus
four point four is considered logic low
so basically it the CMOS is going to
operate in the same way it is just a
level shifting down to a negative
voltages okay so in in this case the
memory okay so you have the full swing
if you have five volt you have a 5 volt
full swing for this operation of the
memory cell array so only the voltage
levels would be negative instead of
positive okay so zero volt would be high
and minus 5 volt would be low okay so
what we shall do in the next class is we
shall study in detail by CMOS static Ram
okay and see how it is realized in in
the how attic Ram can be realized or is
realized in the BI CMOS environment
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Nov 26, 2024 Last updated |
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