All videos of Digital Circuits for Electronics and Communication Engineering (ECE) Exam
Number System
Introduction to Number System
Numericals based on Number System-Part 1
Numericals based on Number System-Part 2
Complement Number Representation
Signed Number Representation for Binary
Important Properties of 1's and 2's Complement Numbers
Concept of Overflow and Sign Extension
Subtraction using r's and (r-1)'s complement method
Conversion of Binary to Gray and Gray to Binary Codes
Gate Numerical on Number System Part 1
Gate Numerical on Number System Part 2
1 Crore+ students have signed up on EduRev. Have you?
Continue with Google
Download the App
Boolean Algebra
Concept of Minterms and Maxterm
Problems based on Minterms and Maxterms
Complementing the Function
Grouping Techniques in K-Map
Numerical Based on Boolean Algebra
Logic Gates
Numericals based on Universal Logic Gates
Important properties of Ex-OR Gate
Gate Numericals on Logic Gates
Combinational Logic Circuit
Introduction to Combinational Logic Circuit
Implementing Full Adder with Half Adder
4-Bit Parallel/ Ripple Adder
Full Adder using 3:8 Decoder
Decoder using Demultiplexer
Implementing 2:1 Mux using 4:1 Mux
2:1 Multiplexer as Universal Logic Circuit
4:1 Multiplexer as Universal Logic Gate
GATE Problems on Mux, Decoder and Decoder
Sequential Logic Circuit in Digital Circuit
Introduction to Sequential Logic Circuit
Excitation Table for all Latches/Flip Flops
Latch/Flip Flop Conversion Concept
SR Latch to JK Latch Conversion
D Latch to JK Latch Conversion
D Latch to T Latch Conversion
Difference between Latch and Flipflop
Behaviour of Flip Flop in Toggle Mode
Race Around Condition in JK Latch
Master-Slave JK Flip Flop
Introduction to Shift Register
Classification of Shift Register
Introduction to Asynchronous Counter
Asynchronous Down Counter
Asynchronous Up/Down Counter
Introduction To Asynchronous MOD Counter
Designing Asynchronous MOD 10 Counter
Introduction to Synchronous Counter
Designing Synchronous Counter - Part 1
Designing Synchronous Counter - Part 2
Non Overlapping Sequence Detector
Overlapping Sequence Detector
GATE Numericals based on Sequential Logic Circuit
Data Converters
Introduction to ADC and DAC
Concept of Specifications of DAC
Binary Weighted Resistor type DAC
Successive Approximation Register type DAC
Instruction Set Architecture
Introduction Register Organisation Memory Basics
Introduction to Register Set
Single Accumulator Organization: Size 1
Single Accumulator Organization: Purpose 2
Single Accumulator Organization: Connections 3
General Register Organization 1
General Register Organization 2
General Register Organization 3
Instruction Formats: Number of Operands 1
Instruction Formats: Number of Operands 2
Instruction Formats: Number of Operands 3
Instruction Formats: Location of the Operand 1
Instruction Formats: Location of the Operand 2
Instruction Formats: Location of the Operand 3
Instruction Formats: Location of the Operand 4
Instruction Formats: Sub Routine call and Return
Instruction Formats: Register reference instructions
Instruction Formats: I O reference instructions
Model GATE Question On Instruction size
Pipelining
Introduction to Pipelining: Throughput
Introduction to Pipelining: Parallel processing
Pipelining GATE Question 1
Pipelining GATE Question 2
Pipelining GATE Question 3
Pipelining GATE Question 4
Pipelining GATE Question 5
Pipelining GATE Question 6
Pipelining GATE Question 7
Pipelining GATE Question 8
Pipelining GATE Question 9
Pipelining GATE Question 10
Pipelining GATE Question 11
Pipelining GATE Question 12
Pipelining GATE Question 13
Pipelining GATE Question 14
Pipelining GATE Question 15
Pipelining GATE Question 16