Test: Asynchronous Counter - 1 - Electrical Engineering (EE) MCQ

Concept:

For the n-stage ripple counter, the no. of flip-flops used are n.

If Each flip flop is having propagation delay of t_p seconds.

Then overall propagation delay of the n-stage ripple counter is 'nt_p'

Both of the above diagrams is a 3 stage up counter.

i.e., 3 flip-flops are used.

In order to obtain Q₂, the 3 clocks will be used at a different instant or at the instant when each flip flop will get their input.

If each flip flop is having 't_p' as propagation delay, then to get output, the overall propagation Delay will be sum of the propagation Delay of each flip flop.

Explanation:

Given

Ripple counter 4 flip flop 

t_p = 20 n second for each flip flop.

T = n t_p = total propagation delay

⇒ T = 4 × 20 n sec = 80 n sec

Clock frequency = 

Concept:

For the MOD-N asynchronous counter, the number of T flip-flops is given by:

MOD-N ≼ 2^N 

where N = No. of flip-flops

Calculation:

MOD 10 ≼ 2N 

N = 4

Therefore, the number of T flip-flops required to realize a mod-10 asynchronous counter is 4.

Concept:

Counters are characterized by the clock connection & triggering of the clock, as explained below:

Analysis:

• In the given circuit, each of the JK flip-flops is negative edge triggered & the clock connection is with ‘Q’. So it is an up counter.
• The output of each flip-flop will be cleared i.e 0 Only when the output from the NAND gate is '0'. So, to get we have to obtain the outputs from flip-flops 2nd,3rd & 4rth as '1' i.e Q₄, Q₃, Q₂ = 1
• So when Q₄, Q₃ & Q2 simultaneously are equal to 1 for the first time, the counter will reset.

So, the sequence of counter states for consecutive clock pulses are as follows:

Here Q_4, Q₃ & Q₂ will be ‘1’ simultaneously for the first time after 28^th Clock Pulse is what we observe.

So the given counter is a mode-28 up counter because it can show up in only 28 states.

Delay Problem:

• In asynchronous counters, the output of the previous stage serves as the clock of the next stage.
• As the number of stages increases the propagation delay of each flip flop stage adds up resulting in the propagation delay to become significant.

The remedy of Propagation delay:

• To eliminate the propagation delay encountered in different stages, all the flip flops are provided with a common clock (Synchronous Counters).
• Thus, the output of each stage does not depend on the clock from the previous stage but only on the common clock signal and propagation delay does not add.

Ripple Counter :

For a ripple counter if the number of flip flops is 'n' then total states are 2n and MOD is 2n 

BCD Counter :

A BCD counter counts 10 states from 0 to 9 

It is MOD 10 counter 

Number of flips required 4 

Ring counter:

A n bit ring counter counts n states and mod is "n"

Johnson Counter:

A n bit Johnson ring counter has 2n states and the mod is 2n

Ripple counter: (negative edge)

In a ripple counter using edge triggered JK flip-flops, the pulse input is applied to clock input of one flip-flop. 

A ripple counter requires maximum propagation delay for counting therefore increasing the number of circuits for every count exceeded.

For a counter with ‘n’ flip flops:

• The total number of states = 2n (0 to 2n – 1)
• The largest number that can be stored in the counter = 2n – 1

To construct a counter with any MOD number, the minimum number flip flops required must satisfy:

Modulus ≤ 2n

Where n is the number of flip-flops.

Calculation:

For a Modulo-N counter, which can count to a total of N-states, the number of flip-flops required is:

N ≥ 2ⁿ

Govem N = 16

So, 16 =  2ⁿ

n = 4

So, the number of J-K flip-flops in Modulo-16 binary up-counter is 4.

Concept:

For an n-bit ripple counter, the MSB is generated only when the carry form all the pervious flip-flip are propagated to the MSB flip flop.

So, the maximum time(Worst-Case delay) taken for the output of the Ripple counter to be stable = n × t_d (where t_d is the propagation delay of each flip flop) 
        

But in an n-bit synchronous counter, the time taken for the output to be stable is simply the propagation delay of 1 flip-flop i.e. t_d
        

Calculation:

Given n = 8 bit and t_d = 10 ns.

For Ripple counter, the worst-case delay = n × t_b = 8 × 10 ns = 80 nsec.

For Synchronous-Counter the worst-case delay is t_d only, which is 10 ns.

Concept:

For a counter with ‘n’ flip flops:

• The total number of states = 2n (0 to 2n – 1)
• The largest number that can be stored in the counter = 2n – 1

To construct a counter with any MOD number, the minimum number flip flops required must satisfy:

Modulus ≤ 2n

Where n is the number of flip-flops.

Calculation:

Number no. of flip – flops are required to construct a mod-15 counter, must satisfy:

2n ≥ 15 i.e.

n = 4