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Computer Science Engineering (CSE) Exam  >  Computer Science Engineering (CSE) Tests  >  Computer Architecture & Organisation (CAO)  >  Test: CISC & RISC Processors - Computer Science Engineering (CSE) MCQ

Test: CISC & RISC Processors - Computer Science Engineering (CSE) MCQ


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10 Questions MCQ Test Computer Architecture & Organisation (CAO) - Test: CISC & RISC Processors

Test: CISC & RISC Processors for Computer Science Engineering (CSE) 2024 is part of Computer Architecture & Organisation (CAO) preparation. The Test: CISC & RISC Processors questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: CISC & RISC Processors MCQs are made for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: CISC & RISC Processors below.
Solutions of Test: CISC & RISC Processors questions in English are available as part of our Computer Architecture & Organisation (CAO) for Computer Science Engineering (CSE) & Test: CISC & RISC Processors solutions in Hindi for Computer Architecture & Organisation (CAO) course. Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free. Attempt Test: CISC & RISC Processors | 10 questions in 10 minutes | Mock test for Computer Science Engineering (CSE) preparation | Free important questions MCQ to study Computer Architecture & Organisation (CAO) for Computer Science Engineering (CSE) Exam | Download free PDF with solutions
Test: CISC & RISC Processors - Question 1
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The CISC stands for ___________

Detailed Solution for Test: CISC & RISC Processors - Question 1

Answer: d
Explanation: CISC is an computer architecture where in the processor performs more complex operations in one step.

Test: CISC & RISC Processors - Question 2
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The computer architecture aimed at reducing the time of execution of instructions is ________

Detailed Solution for Test: CISC & RISC Processors - Question 2

Answer: b
Explanation: The RISC stands for Reduced Instruction Set Computer.

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Test: CISC & RISC Processors - Question 3
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 The Sun micro systems processors usually follow _____ architecture.

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The Risc machine aims at reducing the instruction set of the computer.

Test: CISC & RISC Processors - Question 4
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The RISC processor has a more complicated design than CISC. 
Detailed Solution for Test: CISC & RISC Processors - Question 4

Answer: b
Explanation: The RISC processor design is more simpler than CISC and it consists of fewer transistors.

Test: CISC & RISC Processors - Question 5
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The iconic feature of the RISC machine among the following are
Detailed Solution for Test: CISC & RISC Processors - Question 5

Answer: c
Explanation: A branch delay slot is an instruction space immediately following a jump or branch.

Test: CISC & RISC Processors - Question 6
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Both the CISC and RISC architectures have been developed to reduce the ______
Detailed Solution for Test: CISC & RISC Processors - Question 6

Answer: c
Explanation: The semantic gap is the gap between the high level language and the low level language.

Test: CISC & RISC Processors - Question 7
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Out of the following which is not a CISC machine.
Test: CISC & RISC Processors - Question 8
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Pipe-lining is a unique feature of _______
Detailed Solution for Test: CISC & RISC Processors - Question 8

Answer: a
Explanation: The RISC machine architecture was the first to implement pipe-lining.

Test: CISC & RISC Processors - Question 9
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 In CISC architecture most of the complex instructions are stored in _____
Detailed Solution for Test: CISC & RISC Processors - Question 9

Answer: d
Explanation: In CISC architecture more emphasis is given on the instruction set and the instructions take over a cycle to complete.

Test: CISC & RISC Processors - Question 10
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Which of the architecture is power efficient?
Detailed Solution for Test: CISC & RISC Processors - Question 10

Answer: b
Explanation: Hence the RISC architecture is followed in the design of mobile devices.

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