Test: CMOS - 2 - Electrical Engineering (EE) MCQ

M1 will be in linear region if V_out>V_in + V_T

At the edge of the linear region V_out= V_in + V_T


So, for Vin< 2.5 the PMOS will be in a linear region so the correct option is (1)

The circuit of a CMOS Logic circuit is as shown:

• It is a simple single dynamic CMOS with Precharge phase CLK = 0 and Evaluate phase CLK = 1.
• When no clock signal is applied, CMOS Logic circuit falls under static circuits in which every point in time, each gate output is connected to either VDD or VSS.
• A static CMOS logic circuit is a combination of two networks, called the pull-up-network (PUN) & pull-down-network (PDN) as shown:
  

C is the clock signal
Consider C = 1
The truth table is


→ A = 1 and B = 1 is Forbidden
Whenever A = 1, Y = 0
Yn+1 = 0
Whenever B = 1, X = 0
XN+1 = 0
X = Q output
Y = Q̅ output
B = Reset (R)
A = Set (S)

Concept:
Static power is proportional to the static current, i.e. the current that flows regardless of gate switching.
Dynamic Power is related to the current that flows when switching takes place and is given by for CMOS as:

P = fCV²_cc
Or P = Kf (where K = V_cc²C)
Power consumed by CMOS = P_static + P_dynamic

Calculation:
For f₁ = 10MHz, Pconsumed = 100 mW = P₁ (Let)
For f₂ = 15MHz, Pconsumed = 140 mW = P₂
⇒ P₁ = P_static + P_dynamic
⇒ 100 mW = P_static + Kf₁
⇒ 100 mW = P_static + K(10 M) …1)
Similarly, P₂ = 140 mW = P_static + K(15 M) …2)
From equation (i) and (ii)
P_static = 20 mW

CMOS is a combination of NMOS & PMOS.
NAND gate can be implemented using two PMOS in parallel and two NMOS in series as shown:

Observations:

• When VA & VB are high at +VDD (5V), then the PMOS will be open-circuited and two NMOS will be short-circuited, the output will be short-circuited to ground and produces a Zero (0V) output.
• When any of the input is low (0 V), the corresponding PMOS will be shorted and NMOS will be open, the output is shorted to VDD, i.e. it produces a high output.

NAND Gate:

It is the combination of AND Gate followed by NOT Gate.
When the two inputs A and B are high, then output y is low, otherwise, it is high.

⇒ If P = high:
PMOS is OFF
NMOS is ON 
then y = Q̅
⇒If P = low
PMOS is ON
NMOS is OFF 
then  y = Q
The truth table of the above will be as shown:

So, Ex – OR Operation is being performed.

In large scale integration (LSI), CMOS (complementary Metal-oxide Semiconductor) circuit takes the less Chip area during fabrication. This is because the CMOS circuit is a combination of NMOS and PMOS and it is fabricated as a twin tub process where the required Chip area is less.
During the process of bipolar logic families (such as RTL, DTCL, DTL, HTL, TTL, and ECL) fabrication, required large chip area as these circuits consist of NPN and PNP transistor, diodes, resistors, etc.
Important Comparison between bipolar logic circuits and MOS logic circuits:

Inverter

• This is equal to NOT gate in the digital circuitry.
• The output of this is a compliment of the input.

This can be built from the transistors like BJT, MOSFET, etc…

The CMOS inverter consists of the NMOS and the PMOS field-effect transistors connected in one below the other.

When In = Low
PMOS will be shorted and output will be High.
When In = High
NMOS will be shorted and output will be Low.
Hence it acts as an inverter.

Concept:

• Feature Size: The minimum feature size is the size or the width at which a transistor or any type of material on the silicon surface can be drawn at.
• If the minimum feature size can be reduced, this means that the transistor length can be reduced effectively making the transistor smaller with the same electrical properties.
• This allows for lower current flow between the junction for the same purpose and lesser heat dissipation.

The minimum line width is 2 × minimum feature size  ---(1)

Calculation:
Given:
Minimum feature size = 25 μm
Now the minimum line width can be calculated from equation (1)
Minimum line width = 2 × 25 μm
Minimum line width = 50 μm 
Hence option (3) is the correct answer.

Concept:
Complementary Metal-oxide-semiconductor (CMOS) uses complementary & symmetrical pair of P-type & n-type MOSFETS.

• The two important characteristics of CMOS devices are high noise immunity and low power dissipation.
• In CMOS, during static operation at a time, only one MOS is ON i.e. either PMOS or NMOS. So there is no direct path from the power supply to the ground. Hence, Power dissipation in CMOS is low in static operation but it has high power dissipation in dynamic operation.

Calculation:
As the given figure is of CMOS with two inputs.

The upper part is PMOS which is switched on when 0 is applied and NMOS is switched on when 1 is applied.

 

• When S = 0 is applied, the PMOS connected to S (upper one) will be shorted and P at PMOS will appear across the output in complemented form as shown in fig(A).
  So Output = P̅
• Now when S = 1 is applied, the NMOS connected to S (lower one) will be shorted, and due to which ground will appear across the output and the circuit will go in a high impedance state as shown in fig(B).

Hence option (2) is the correct answer.