Test: Combinational Logic Circuits - Electrical Engineering (EE) MCQ

The logic gate for traffic control is:

For red light
Output X = NOT (J)

For yellow light
Output Y = K

For green light:
Output Z = J AND (NOT K)

Combined Circuit is given as,

Now, all the gates can be formed from NAND gate, as it is a universal gate. 
NAND gate will be the correct answer. 

Multiplexers:

• A multiplexer is a combinational circuit.
• A multiplexer is Many to one data selector.
• A multiplexer selects one of the many data available at its input depending on the bits on the select line.
• For 2n inputs, there are n select lines that determine, which input is to be connected to the output.

A 2-input multiplexer is as shown below.

Output, Y = D₀S̅ + D₁S

Combinational Logic circuits:
Combinational Logic circuits are circuits for which the present output depends only on the present input, i.e. there is no memory element to store the past output.
A combinational circuit can have ‘n’ number of inputs and ‘m’ number of outputs as shown:

Combinational circuits are:

• Multiplexer/Demultiplexer
• Encoder/Decoder
• Adders
• Subtractors
• Code Converters

Multiplexers:

• A multiplexer is Many to one data selector.
• A multiplexer selects one of the many data available at its input depending on the bits on the select line.
• For 2m inputs, there are m select lines that determine which input is to be connected to the output.

Concept:
A universal gate is the one with which any other Boolean function can be implemented without the need of other gates.
Two universal gates are NAND and NOR.
NAND:
In this gate, output of logic gate is false only when both the inputs are true. It is the complement of AND gate.
NOR gate: Output of this logic gate is true when both inputs are false.
Truth Table:

• A half adder is also known as XOR gate because XOR is applied to both inputs to produce sum
• Half adder can add only two bits (A and B) and has nothing to do with the carry
• If the input to a half adder has a carry, then it will neglect it and adds only the A and B bits
• That means the binary addition process is not complete and that's why it is called a half adder

Sum (S) = A⊕B, Carry = A.B

A 64 × 1 multiplexer has 64 inputs so if we use 2 × 1 multiplexers 32 are needed in the first stage for 64 inputs, the output of these 32 multiplexers are connected to inputs of 16 multiplexers in the second stage.
Similarly, in third stage, 8 (2 × 1) multiplexers are used, in fourth stage 4 are used and finally 2 (2 × 1) multiplexers in the fifth stage, 1 in the sixth stage.
Total 2 × 1 multiplexers needed are 32 + 16 + 8 + 4 + 2 + 1 = 63.

ECL (Emitter Coupled Logic):

• It is fast then all logic family and very high speed in ECL transistor use in differential amplifier configuration
• When a transistor is operated in a saturation condition, due to the charge stored in the collector and base regions, it turns ON or OFF slowly. This drawback has been eliminated in ECL by operation the transistor only in the active or off region.

DEMUX:
A demultiplexer (or demux) is a device that takes a single input line and routes it to one of several digital output lines.
It consists of 2n outputs and has n selection lines, which are used to select which output line to send the input. It is also called as a data distributor.

XNOR Gate:
Symbol:

Truth Table:

 

Output Equation: 
Key Points: 
1) If B is always Low, the output is the inverted value of the other input A, i.e. A̅.
2) The output is low when both the inputs are different.
3) The output is high when both the inputs are the same.
4) XNOR gate produces an output only when the two inputs are the same.

The output in a combinational circuit depends on the mixture of input signals present at that moment. It is not determined by the past conditions. The output in a synchronous circuit depends on the mixture of input signals present at that moment and also the past conditions.