GATE Electrical Engineering (EE) Test: Decoders Free Online Test 2026

Concept:

 A decoder is a combinational circuit that converts n lines of input into 2n lines of output.

Decoder expansion

n₁ × m₁ → n₂ × m₂

D₁             D₂

m₂/m₁= K₁

K₁/m₁ = K₂

K₂/m₁ = K₃

Number of D2 decoder required is given as:

∑ K = K₁ + K₂ + K₃ + ------ 

Calculation:

Given decoder 1 is 3 × 8 and the second decoder is 4 × 16

16/8 = 2

2/8 = 0

Number of 3 × 8 decoders = 2 + 0

Number of 3 × 8 decoders = 2

Encoder:

An encoder has 2n input lines and n output lines. In the encoder, the output lines generate the binary code corresponding to the input value which is active high.

Decoder:

It is a multi-input and multi-output logic circuit that converts coded inputs into coded outputs where input and output codes are different. Input code has fewer bits than output code. There is one to one mapping from input to output.

Multiplexer:

It is a digital switch. It allows digital information from several sources to be routed onto a single output line. A basic multiplexer has several data input lines and a single output line. The selection of a particular input line is controlled by selection lines. It is many to one mapping and provides the digital equivalent of an analog selector switch. Therefore it is the correct answer

Demultiplexer:

It is a circuit that receives information on a single line and transmits information on one of the 2n output lines. Selection of output line is controlled by values of n selection lines.

Decoder:

• A decoder is a combinational circuit that has ‘n’ input lines and a maximum of 2n output lines.
• Decoder converts binary-coded information to unique outputs such as decimal, octal digits, etc.
• A particular output will be active High depending upon the combination of inputs present when the decoder is enabled.
• We can, therefore, conclude that a decoder detects a particular code.

A 2 to 4 decoder is shown in the block diagram below:

Truth Table:

Application:

A decoder is used to convert a BCD code to a 7 segment code. This is explained in the following block diagram:

Decoder:

The decoder is a combinational ckt, that convert Binary Coded information into Familiar, representation like the decimal, octal, Hexadecimal, etc.

The decoder has ‘n’ no of i/p & less than equal to 2ⁿ O/P

i.e., n ≤ 2ⁿ
I / P  O / P

For 4 input lines n = 4

Maximum output lines = 2⁴ = 16

Concept:

Decoder expansion

n₁ × m₁ → n₂ × m₂

D₁             D₂

Number of D₂ decoder required = ∑ K

m₂ / m₁ = K₁

K₁ / m₁ = K₂

K₂ / m₁ = K₃

⋮

Till 0 or 1

Calculation:

Given decoder 1 is 3 × 8 and the second decoder is 6 × 64

64 / 8 = 8

8 / 8 = 1

Number of 3 × 8 decoders = 8 + 1

Number of 3 × 8 decoders = 9

Decoder:

Generally, a decoder converts a binary number into any other format (decimal, hexadecimal, etc)

Eg: 2 × 4 decoder

Truth Table:

DeMUX: A demultiplexer takes a single input line and produces many output lines.

Now if we put input pin (I) of DeMUX remains at logic 1 and at select pin of DeMUX (S₁, S₀) we apply i / p (A, B) of decoder then DeMUX will be work as decoder. {I = 1}

Eg:

AB = 00 = S₁ S₀ ;

Y₀ = 1 Y₁ = 0 Y₂ = 0 Y₃ = 0

AB = 10 = S₁ S₀ ;

Y₀ = 0 Y₁ = 0 Y₂ = 1 Y₃ = 0

• In BCD to 7-segment Decoder, the outputs of a digital circuit are often displayed as decimal digits.
• BCD to 7-segment decoder is a combinational circuit that converts a BCD number into signals that are required for the display of the value of that number on a seven-segment display.
• The number of input lines is 4. 

Notes:

• The decoder outputs are (a, b, c, d, e, f, g)
• For the display of the digit 0, segments a, b, c, d, e, f will be lit as shown above.

The given question is the expansion of

2 : 4 decoder to  1 : 8 decoder 

We need to implement 1 : 8 DEMUX.

So, select lines of De-Mux should be mapped to address lines of the decoder.

The LSB of De-Mux should be connected to the LSB of address lines of the decoder

∴ R → S0 

and S→ S₁

Input to both the decoder should be same so

∴ P → D_in

∴ NOT gate along with OR gate in case to select one decoder at a time so Q → S₂ 

So,

P → Din

Q → S2

R → S₀ 

S→ S1

Hence option (D) is correct

To implement 2ⁿ × 1 MUX using 2 × 1 MUX, the total number of 2 × 1 MUX required is (2ⁿ - 1).

∴ The number of 2 × 1 multiplexer required to implement 16 × 1 MUX will be:

n = 16 - 1 = 15

Or we can follow the below steps to calculate the same:

1^st stage = 16/2 = 8

2^nd  stage = 8/2 = 4

3^rd stage = 4/2 = 2

4^th stage = 2/2 = 1

The sum will give the total number of MUX required to implement 16 × 1 multiplexer using 2 × 1, i.e.

n = 8 + 4 + 2 + 1 = 15

Combinational circuit in which output depends only on the state of inputs.

Decoder circuits are constructed from Inverters and AND gates.

8870 is a DTMF decoder circuit, which decodes DTMF tune and produces corresponding output.

Decoder is a circuit with n input lines and 2ⁿ output lines.

BCD to seven segment code conversion can be treated as a decoding process.

For n input lined decoder will have 2ⁿ output lines.