Test: Digital Electronics- 2 - Electronics and Communication Engineering (ECE) MCQ

For the given circuit shown in figure signal generated at the output of AND gat is Y. there clock has signal frequency of 4 kHz, with duty cycle 50%

Q. What is the value of frequency of output Y

The following waveform pattern is for a(n) ________.

Consider the partial implementation of a 2 — bit counter using T flip-flops following the sequence 0 — 2 — 3 — 1 — 0, as shown below.

To complete the circuit, the input X should be 

 For a Flip-flop formed from 2 NAND gates as shown in figure, the unusable state corresponds to

In the figure as long as XI = 1 and X2 = 1 the output Q remains at

The Minimum no. of 2 inputs NAND gate required to implement Boolean function f(A, B, C, D) =

ABCD are_______

The 4 variable function f is given in terms of min term as f(A, B, C, D) = E(2,3,8,10,11,12,14,15)

Q. If by use of K-Map function is minimized in sum of product forms then SOP is

The 4 variable function f is given in terms of min term as f(A, B, C, D) = E(2,3,8,10,11,12,14,15)

Q. Above Minimised SOP, can be implemented by how many min^m no. of 2 input NAND gate.

Consider the following data in respect of a certain digital gate

l_oH = 0.2 mA I_1H= 40μ.A, 10_L = 16 mA, l_iL = 1.6 mA symbols have their meaning. Fan out will be    

If x, y and z are three Boolean variables, then F(x,y,z) = x + xy + y + yz + z + xz is equivalent to

How many AND gates are required for a 1-to-8 multiplexer?

The logic circuit shown in figure is :

In a dual slope ADC if reference voltage is 100 mV and the first integration period is set as 50 msec.

For an input voltage of 120 mV, the second integration (de-integration) period is___ ms

In a dual slope type digital voltmeter, an unknown signal voltage is integrated our 100 cycles of clock. If the signal has a 50 Hz pick up the maximum clock frequency can be__ kHz

In circuit given if both Transistors have same VT what is the approximate value of highest possible output voltage vout if v_h, can range from 0 to V_DD, it is assumed that 0 < v_T < V_DD

In the I.C. logic gate shown in figure.

If threshold voltage V_BE is o.75 volt and V_{CE (sat)} = 0.2 V, calculate. Value of output voltage

Q. If VA = VB = 4.5 volt

For the output F to be 1 in the logic circuit shown, the input combination should be