Test: Karnaugh Maps (K-Maps) - Electronics and Communication Engineering (ECE) MCQ

It is simply a rearranged truth table

The Karnaugh map eliminates the need for using NAND and NOR gates

Variable complements can be eliminated by using Karnaugh maps

A Karnaugh map can be used to replace Boolean rules

NAND 

’ is logically equivalent to what single gate?
A. NAND B. NOR

AND

OR

Symbolic reduction

TTL logic

Using Boolean algebra

Using a truth table

A LOW output for all possible HIGH input conditions

A HIGH output on the truth table for all LOW input combinations

A HIGH for each input truth table condition that produces a HIGH output  

A DON’T CARE condition for all possible input truth table combinations

Variables within the loop that appear only in their complemented form

Variables that remain unchanged within the loop

Variables within the loop that appear in both complemented and uncomplemented form

Variables within the loop that appear only in their uncomplemented form

All logic circuits are reduced to nothing more than simple AND and OR operations

The delay times are greatly reduced over other forms

No signal must pass through more than two gates, not including inverters

The maximum number of gates that any signal must pass through is reduced by a factor of two

A + B = B + A

A • B = B + A

A • (B • C. = (A • B. • C

A • B = B • A

A Karnaugh map

DeMorgan’s second theorem

The commutative law of addition

The associative law of multiplication

A HIGH for each input truth table condition that produces a HIGH output

A HIGH output on the truth table for all LOW input combinations

A LOW output for all possible HIGH input conditions

A DON’T CARE condition for all possible input truth table combinations

Actual circuit trial and error evaluation and waveform analysis

Karnaugh mapping and circuit waveform analysis

Boolean algebra and Karnaugh mapping

Boolean algebra and actual circuit trial and error evaluation