Computer Science Engineering (CSE) Exam > Computer Science Engineering (CSE) Tests > Question Bank for GATE Computer Science Engineering > Test: Logic Family & Memories- 2 - Computer Science Engineering (CSE) MCQ
Test: Logic Family & Memories- 2 - Computer Science Engineering (CSE) MCQ
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6 Questions MCQ Test Question Bank for GATE Computer Science Engineering - Test: Logic Family & Memories- 2
Test: Logic Family & Memories- 2 for Computer Science Engineering (CSE) 2024 is part of Question Bank for GATE Computer Science Engineering preparation. The Test: Logic Family & Memories- 2 questions and answers have been
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Test: Logic Family & Memories- 2 - Question 1
The refreshing rate of dynamic RAMs is approximately once in
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Test: Logic Family & Memories- 2 - Question 2
The number of bits that are typically stored on each track of a magnetic disk is usually
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Test: Logic Family & Memories- 2 - Question 3
The figure of merit of a logic family is given by
Test: Logic Family & Memories- 2 - Question 4
A memory system of size 16 K bytes is required to be designed using memory chips which have 12 address lines and 4 data lines each. The number of such chips required to design the memory system is:
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Test: Logic Family & Memories- 2 - Question 5
The advantage of MOS devices over bipolar devices is that
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