Test: S-R Flip Flop - Electrical Engineering (EE) MCQ

Concept:

The maximum no. of states that can be represented by N flip-flops is given by:

No. of states = 2^N

Calculation:

Given, N = 3

No. of states = 2³ = 8

The states from 0 to 7 are represented by 3 flip-flops.

 The maximum binary number is 111

An un-clocked R-S flip flop using NOR gates is as shown:

The truth table for the circuit is shown:

The given sequential component is of RS Flip Flop.

Here A = R and B = S

The truth table for the circuit is shown:

Latches and Flip-Flop:

• Latches and flip-flops are the basic elements to store 1-bit of data. Hence they are also known as a one-bit memory element.
• Latches change the output continuously when there is a change in the input, i.e. they are level triggered.
• Flip-flop is a combination of latch and clock. It changes the output that is adjusted by the clock.
• The main difference between a latch and a flip-flop is that a flip-flop has a clock signal, whereas a latch does not.
• We can say that a flip-flop without a clock is a latch.
• Latches are asynchronous, which means that the output of a latch depends on its input.
• Basically, there are 4 types of latches: SR latch, JK latch, D latch, T latch.

In J-K flip flop when both inputs are HIGH, the output toggles i.e. it changes from high to low and low to high periodically when both the inputs are 1.
For an SR flip flop, however, when both the inputs are HIGH, we encounter an invalid state, which is not present for a JK flip flop.
This is explained with the help of the following function table:

​Similarly, for a JK flip flop, the block diagram along with the function table is as shown:

Features that distinguish:

a) When both S and R inputs are 1, output goes to a metastable state but when both the inputs of J and K are 1 output is in toggle state with respect to the previous state.

b) JK flip flop is often termed as Universal flip flop because all other flips like D, T, and SR can be derived from that while this is not the case with respect to SR flip flops.

c) SR flip flops when used as latch can be helpful in the bounce elimination of the switches which is one of its major advantages while this is not the case with JK flip flops.

SR flip flop: 

Characteristic Table of SR flip flop

Qn+1 = S + R̅ Qn

JK flip flop:

Characteristic Table of JK flip flop

Qn+1 = JQ̅n + K̅Qn

The implementation of JK flip flop from SR latch is shown.

The truth table for SR flip flop is given as

From the truth-table, we can see if the two inputs S and R are 0 0, then the output remains in the previous state. So, if Q_n = High then Q_n+1 = High

A NAND gate latch circuit, from the truth table we get

For low inputs, the output will be Unpredictable.

The circuit is a SR flip-flop with input A = S and B = R. In SR flip-flop there is no race around condition for any combination of input.

Note :

11 is a not allowed state because the output Q and Q'  will be 1. 

For race around Q should toggle.

It occurs in JK flip flop when J=K=1 and there is unequal propagation delay.

Concept:

Counters:

• It is a sequential logic circuit that has a clock input signal and a group of output signals
• It represents an integer "counts" value.
• Internally, counters use flip-flops to represent the current counts and to retain the counts between clocks.
• N values can be counted with n number of flip flops. its relation is given by-

2ⁿ ≥ N

where, N = number of counts

n = number of flip flops

Calculation-

Given- N= 1023

 2ⁿ ≥ 1023

 n = 10

 Hence total of 10 flip flops are required to count from 0 to 1023.

An un-clocked R-S flip flop using NOR gates is as shown:

The truth table for the circuit is shown:

An unclocked R-S flip flop using NOR gates is as shown:

The truth table for the circuit is shown:

When the S and R inputs of an SR flipflop are at logical 1, then the output becomes unstable and it is known as a race condition. 

So, the main disadvantage of the SR flip flop is invalid output when both inputs are high. 

An edge-triggered flip-flop change states either at the positive edge (rising edge) or at the negative edge (falling edge) of the clock pulse on the control input.

A negative edge triggered flip flop transfers data from input on the high to low transition of the clock pulse.

The cross-coupled connections from the output of one gate to the input of the other gate constitute a feedback path. For this reason, the circuits of NOR based S-R latch classified as asynchronous sequential circuits. Moreover, they are referred to as asynchronous because they function in the absence of a clock pulse.

The basic S-R flip-flop can be constructed by cross coupling of NOR or NAND gates. Cross coupling means the output of second gate is fed to the input of first gate and vice-versa.