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Test: Secondary Memory & DMA- 1 - Computer Science Engineering (CSE) MCQ


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7 Questions MCQ Test GATE Computer Science Engineering(CSE) 2025 Mock Test Series - Test: Secondary Memory & DMA- 1

Test: Secondary Memory & DMA- 1 for Computer Science Engineering (CSE) 2024 is part of GATE Computer Science Engineering(CSE) 2025 Mock Test Series preparation. The Test: Secondary Memory & DMA- 1 questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: Secondary Memory & DMA- 1 MCQs are made for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Secondary Memory & DMA- 1 below.
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Test: Secondary Memory & DMA- 1 - Question 1

 During DMA transfer, DMA controller takes over the buses to manage the transfer

Detailed Solution for Test: Secondary Memory & DMA- 1 - Question 1

During DMA transfer, DMA controller takes over the busses to manage the transfer directly from I/O devices to memory or vice-versa.

Test: Secondary Memory & DMA- 1 - Question 2

Which of the following data transfer mode takes relatively more time?

Detailed Solution for Test: Secondary Memory & DMA- 1 - Question 2

Programmed I/O data transfer mode takes relatively more time than DMA and interrupt initiated I/O.

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Test: Secondary Memory & DMA- 1 - Question 3

 The CPU initializes the DMA by sending ______ .

Detailed Solution for Test: Secondary Memory & DMA- 1 - Question 3

The CPU initializes the DMA by sending:
The starting address of the memory blocks where data are available (for read) or where data are to be stored. (For write)
The word count, which is the number of words in the memory.
Control to specify the mode of transfer such as read or write.

Test: Secondary Memory & DMA- 1 - Question 4

Assembler directives represents_______ .
1. Machine instruction to be included in the object program.
2. The allocation of storage for constants or program variable.

Detailed Solution for Test: Secondary Memory & DMA- 1 - Question 4

Assembler directives neither represents machine instructions to be included in the object program nor indicate the allocation of storage for constants or program variables.
Instead, these statements direct the assembler to take certain actions during the process of assembling a program. They are used to indicate certain things regarding how assembly of the input program is to be performed.

Test: Secondary Memory & DMA- 1 - Question 5

Daisy Chained and Independent Request bus arbitration requires______respectively. (Where N stands for number of Bus Master Devices in the Configuration)

Detailed Solution for Test: Secondary Memory & DMA- 1 - Question 5

Daisy chained arbitration scheme requires 3 lines irrespective of the number of devices, A pair of REQ/GRANT lines are required in the case of independent request type arbitration and so for N devices 2N lines

Test: Secondary Memory & DMA- 1 - Question 6

Select the correct option for communication between computer buses with memory and I/O.

Detailed Solution for Test: Secondary Memory & DMA- 1 - Question 6

For communication between can:
1. Contain one common bus for memory and I/O with common control lines.
2. Contain two separate buses, one for memory and other for I/O.
3. Contain one common bus for memory and I/O but have separate control line for each.

Test: Secondary Memory & DMA- 1 - Question 7

A processor that communicates with remote terminals over telephone and other communication media in a serial fashion is called _______ .

Detailed Solution for Test: Secondary Memory & DMA- 1 - Question 7

Data communication processor is the processor that communicate with remote terminals over telephone and other communication media in a serial fashion.

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