Computer Science Engineering (CSE) Exam > Computer Science Engineering (CSE) Tests > Computer Architecture & Organisation (CAO) > Test: Single BUS Organisation 1 & 2 - Computer Science Engineering (CSE) MCQ
Test: Single BUS Organisation 1 & 2 - Computer Science Engineering (CSE) MCQ
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20 Questions MCQ Test Computer Architecture & Organisation (CAO) - Test: Single BUS Organisation 1 & 2
Test: Single BUS Organisation 1 & 2 for Computer Science Engineering (CSE) 2024 is part of Computer Architecture & Organisation (CAO) preparation. The Test: Single BUS Organisation 1 & 2 questions and answers have been
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Detailed Solution for Test: Single BUS Organisation 1 & 2 - Question 1
Test: Single BUS Organisation 1 & 2 - Question 2
A common strategy for performance is making various functional units operate parallely.
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Detailed Solution for Test: Single BUS Organisation 1 & 2 - Question 3
Test: Single BUS Organisation 1 & 2 - Question 4
Which register in the processor is single directional ?
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Test: Single BUS Organisation 1 & 2 - Question 7
The registers,ALU and the interconnecting path together are called as ______
Test: Single BUS Organisation 1 & 2 - Question 8
The input and output of the registers are governed by __________
Test: Single BUS Organisation 1 & 2 - Question 9
When two or more clock cycles are used to complete data transfer it is called as ________
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Test: Single BUS Organisation 1 & 2 - Question 10
________ signal is used to show complete of memory operation.
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Test: Single BUS Organisation 1 & 2 - Question 11
Is the below code segment correct, for the addition of two numbers ?
R1in, Yin
R2out, Select Y, ADD , Zin
Zout, R3in
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Test: Single BUS Organisation 1 & 2 - Question 12
The completion of the memroy operation is indicated using ______ signal.
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Test: Single BUS Organisation 1 & 2 - Question 13
_________ signal enables the processor to wait for the memory operation to complete.
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Test: Single BUS Organisation 1 & 2 - Question 14
The small extremly fast, RAM’s all called as ________
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Test: Single BUS Organisation 1 & 2 - Question 15
The main virtue for using single Bus structure is
Test: Single BUS Organisation 1 & 2 - Question 16
To extend the connectivity of the processor bus we use ______
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Test: Single BUS Organisation 1 & 2 - Question 17
The bus used to connect the monitor to the CPU is
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Test: Single BUS Organisation 1 & 2 - Question 18
The ISA standard Buses are used to connect ___________
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Test: Single BUS Organisation 1 & 2 - Question 20
IBM developed a bus standard for their line of computers ‘PC AT’ called
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