Test: Combinational Logic Circuits- 2 - Railways MCQ

The truth table for the given problem is shown below:

The K-map for the above truth table is shown below:

Thus output, Y = CD₃ + CD₂ + CD₁
= C(D₁ + D₂ + D₃)

Let us consider D for door, I for ignition and L for light. Then, conditions to activate the alarm are:
(i) The headlights are ON while the ignition is OFF
i.e. L = 1, I = 0 and D may be anything.
(ii) The door is open while the ignition is ON. i.e. D = 1 , I = 1, L may be anything.
Also, alarm will sound if logic circuit output is zero.
Therefore, output (V) for above condition is zero and for rest of the condition it is 1 which is shown in following truth table.

K-map for above truth table is shown below.

Thus, the output of the given logic circuit is

Invalid BCD inputs are from decimal 10 to 11. The K-map is shown below:

Thus, output F = AB + AC, which can be implemented using three 2-input NAND gates as shown below,.

 

Let the binary inputs to be added be (A₄ A₃ A₂ A₁) and (B₄ B₃ B₂ B₁). A 4-bit adder using cascade connection of four 1-bit full adder is shown below. Here, C represents for carry and Sfor sum.

It is clear from above circuit that each addition requires 80 ns.
Therefore, maximum number of additions that can be performed by this 4-bit adder

= 125 x 10⁵ additions/sec

Let the two inputs variations be Xand Y.
EX-NOR gate using 2 x 1 MUX:

Here, we require two 2 x 1 MUX.
NAND g a te using 2 x 1 MUX:

Thus, we require two number of 2 x 1 MUX for NAND gate implementation.

Output,

= EX-NOR gate

Given, logic expression is
f(A, B, C) = πM(0,3,5) = ∑m(1,2, 4, 6,7).
Here, B and C has to be control inputs while A as data inputs. We form the table as shown below:

Thus,

A full adder is used to add three input bits (A, R and C) to give two outputs namely sum and carry as shown below:

For its implementation we require either of the following:

• One 3 x 8 decoder and two OR gates.
• Two half adders and one OR gate.
• Nine NAND/NOR gates.

To add two n-bit numbers using parallel adder circuit, we require
(n - 1) full adders and 1-half adder
or
n-full adders
or
(2n -1) half adders and (n - 1) OR gates Thus, to add two 4-bit numbers using parallel adder circuit, we require
3- full adder and 1 -half adder
or
4- full adders
or
7-half adder and 3 OR gates
Hence, option (d) is correct.

The correction to be applied in decimal adder to the generated sum is 00110. When the four bit sum is more than 9, then the sum is invalid, in such cases, +6 (i.e. 0110) is added to the four bit sum to skip the six invalid states, if a carry is generated when adding 6, the carry is added to the next four bit group.

The gates required to build a half adder are EX-OR gate and AND gate. Figure below shows the logic diagram of half adder.

The code where all successive numbers differ from their preceding number by single bit is Gray code. (It is an unweighted code. The most important characteristic of this code is that only a single bit change occurs when going from one code number to next).

The device which changes from serial data to parallel data is demultiplexer because it takes in data from one line and directs it to any of its A/outputs depending on the status of the select inputs.

A decoder converts binary words into alphanumeric characters i.e. it converts BCD to seven segment.

From given circuit, we have:
 y₁ = x₁

Thus, the given circuit will convert binary code x₁, x₂, x₃ into Gray code y₁ y₂ y₃.

From given circuit, output is

In even parity generator if number of ‘1’ is odd then output wifi be zero. Here, input 0111 has odd number of 1's, therefore output of even parity generator will be zero.