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Computer Science Engineering (CSE) Exam  >  Computer Science Engineering (CSE) Tests  >  Computer Architecture & Organisation (CAO)  >  Test: Direct Memory Access - Computer Science Engineering (CSE) MCQ

Test: Direct Memory Access - Computer Science Engineering (CSE) MCQ


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15 Questions MCQ Test Computer Architecture & Organisation (CAO) - Test: Direct Memory Access

Test: Direct Memory Access for Computer Science Engineering (CSE) 2025 is part of Computer Architecture & Organisation (CAO) preparation. The Test: Direct Memory Access questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: Direct Memory Access MCQs are made for Computer Science Engineering (CSE) 2025 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Direct Memory Access below.
Solutions of Test: Direct Memory Access questions in English are available as part of our Computer Architecture & Organisation (CAO) for Computer Science Engineering (CSE) & Test: Direct Memory Access solutions in Hindi for Computer Architecture & Organisation (CAO) course. Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free. Attempt Test: Direct Memory Access | 15 questions in 15 minutes | Mock test for Computer Science Engineering (CSE) preparation | Free important questions MCQ to study Computer Architecture & Organisation (CAO) for Computer Science Engineering (CSE) Exam | Download free PDF with solutions
Test: Direct Memory Access - Question 1
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The DMA differs from the interrupt mode by

Detailed Solution for Test: Direct Memory Access - Question 1

Answer: d
Explanation: DMA is an approcah of performing data transfers in bulk between memory and the external device without the intervention of the processor.

Test: Direct Memory Access - Question 2
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The DMA transfers are performed by a control circuit called as

Detailed Solution for Test: Direct Memory Access - Question 2

Answer: b
Explanation: The Controller performs the functions that would normally be carried out by the processor.

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Test: Direct Memory Access - Question 3
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 In DMA transfers, the required signals and addresses are given by the

Detailed Solution for Test: Direct Memory Access - Question 3

Answer: c
Explanation: The DMA controller acts like a processor for DMA transfers and overlooks the entire process.

Test: Direct Memory Access - Question 4
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 After the complition of the DMA transfer the processor is notified by
Detailed Solution for Test: Direct Memory Access - Question 4

Answer: b
Explanation: The controller raises an interrupt signal to notify the processor that the transfer was complete.

Test: Direct Memory Access - Question 5
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The DMA controller has _______ registers
Detailed Solution for Test: Direct Memory Access - Question 5

Answer: c
Explanation: The Controller uses the registers to store the starting address,word count and the status of the operation.

Test: Direct Memory Access - Question 6
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When the R/W bit of the status register of the DMA controller is set to 1.
Test: Direct Memory Access - Question 7
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The controller is connected to the ____
Detailed Solution for Test: Direct Memory Access - Question 7

Answer: b
Explanation: The controller is directly connected to the system BUS to provide faster transfer of data.

Test: Direct Memory Access - Question 8
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Can a single DMA controller perform operations on two different disks simulteneously? 
Detailed Solution for Test: Direct Memory Access - Question 8

Answer: a
Explanation: The DMA controller can perform operations on two different disks if the appropriate details are known.

Test: Direct Memory Access - Question 9
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The techinique whereby the DMA controller steals the access cycles of the processor to operate is called
Detailed Solution for Test: Direct Memory Access - Question 9

Answer: c
Explanation: The controller takes over the processor’s access cycles and performs memory operations.

Test: Direct Memory Access - Question 10
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The technique where the controller is given complete access to main memory is
Detailed Solution for Test: Direct Memory Access - Question 10

Answer: d
Explanation: The controller is given full control of the memory access cycles and can transfer blocks at a faster rate.

Test: Direct Memory Access - Question 11
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The controller uses _____ to help with the transfers when handling network interfaces.
Detailed Solution for Test: Direct Memory Access - Question 11

Answer: a
Explanation: The controller stores the data to transfered in the buffer and then transfers it.

Test: Direct Memory Access - Question 12
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To overcome the conflict over the possession of the BUS we use ______
Detailed Solution for Test: Direct Memory Access - Question 12

Answer: b
Explanation: The BUS arbitrator is used overcome the contention over the BUS possession.

Test: Direct Memory Access - Question 13
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The registers of the controller are ______
Test: Direct Memory Access - Question 14
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When process requests for a DMA transfer
Detailed Solution for Test: Direct Memory Access - Question 14

Answer: d
Explanation: The process requesting the transfer is paused and the operation is performed , meanwhile another process is run on the processor.

Test: Direct Memory Access - Question 15
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The DMA transfer is initiated by _____
Detailed Solution for Test: Direct Memory Access - Question 15

Answer: c
Explanation: The transfer can only be initiated by instruction of a program being executed.

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Direct Memory Access MCQs with Answers

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