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GATE Mock Test Electronics Engineering (ECE)- 9 - Electronics and Communication Engineering (ECE) MCQ


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65 Questions MCQ Test GATE ECE (Electronics) 2024 Mock Test Series - GATE Mock Test Electronics Engineering (ECE)- 9

GATE Mock Test Electronics Engineering (ECE)- 9 for Electronics and Communication Engineering (ECE) 2024 is part of GATE ECE (Electronics) 2024 Mock Test Series preparation. The GATE Mock Test Electronics Engineering (ECE)- 9 questions and answers have been prepared according to the Electronics and Communication Engineering (ECE) exam syllabus.The GATE Mock Test Electronics Engineering (ECE)- 9 MCQs are made for Electronics and Communication Engineering (ECE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for GATE Mock Test Electronics Engineering (ECE)- 9 below.
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GATE Mock Test Electronics Engineering (ECE)- 9 - Question 1

A invest 1/3 part of the capital for 1/6 of the time, B invest 1/4 part of the capital for 1/2 of the time and C invest rest of the capital for rest of the time. Out of a profit of Rs. 23000, B’s share is?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 1
Raio of their Investment

= 4 : 9 : 10

B’s share = 23000 x 9/23 = Rs.9000

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 2

Pick the odd one out.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 2
Swimming is done in a large water body. All the other words relate to activities involving smaller volume of water.
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 3

In the following question, out of the four alternatives, select the word opposite in meaning to the given word.

Gratuitous

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 3
The word “gratuitous” means given or done free of charge. Thus, the word “costly” would be the correct antonym of the given word.

Gratis means without charge; free. Thus, option B is the correct answer.

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 4

Pick the odd one out.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 4
Break, hiatus and pause, all mean a temporary halt. End is the final halt.
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 5

The bar graph shows the number of employees working under the six different Departments (A, B, C, D, E, F) of a certain company. Study the diagram and answer the following questions.

If departments F and D are merged to create a new department G, then which department will have the least number of employees?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 5

If departments F and D are merged to create a new department G, then

Employees in department A = 25

Employees in department B = 6

Employees in department C = 10

Employees in department E = 15

Employees in department G = 8

∴ Department B has the least number of employees

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 6

Fill in the missing number in the series:

7, 13, 21, ____, 43, 57

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 6
In this series, each subsequent term is obtained by adding 6, 8, 10, 12, 14,... respectively in the previous term. Hence, the missing term is 21 + 10 = 31.
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 7

A sum of Rs.400 amounts to Rs.480 in 4 years. What will it amount to if the rate of interest is increased by 2 % for the same time?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 7

We know that,

A = S.I + P

480 = S.I + 400

⟹ S.I = 480 – 400 = 80

⟹ S.I =

⟹ 80 =

⟹ R = 5 %

Now rate is increased by 2 %

So, new rate is 7%

New S.I = = Rs. 112

New Amount = S.I + P = 112 + 400 = Rs.512

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 8

How many times do the hands of a clock overlap in 24 hours?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 8
After 11 o'clock, the minute hand has to travel all the way and by the time they meet it is has to be 12 o'clock again, since we know what the clock looks like at that time. So the two hands overlap 11 times in a 12 hour period. So, in a 24 hour period, they would overlap 22 times.
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 9

In the following question, some part of the sentence may have errors. Find out which part of the sentence has an error and select the appropriate option. If the sentence is free from error, select 'No error'.

The gold foil used liberal (1)/ in Thanjavur paintings serves (2)/ many objectives that makes the painting more attractive. (3)/ No error

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 9
The error is in part (1) of the sentence. Change ‘liberal’ to ‘liberally’ because in this sentence it is in adjective form while the proper usage of liberal is in its adverb form i.e. ‘liberally’ as it qualifies the gold foil here.
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 10

In the following question, a group of four figures following certain sequence is given as problem figures. Problem figures are followed by another group of four figures known as answer figures marked (1), (2), (3), (4). Find out the figure from the answer figures which when placed next to the problem figures will continue the sequence of the problem figures.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 10
In going from one problem figure to the next, the arrows are going from vertical to horizontal and one arrow decreases in number.

Then they again go back to vertical.

Answer figure (3) will continue the sequence of the problem figures.

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 11

During transmitting over a binary communication channel, bit error occurs independently with a probability of p. The probability of at most 2 bits in error in a block of ‘n’ transmitted bits would be

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 11
Probability of no error = (1 - p)n

Probability of single bit in error = nC1p(1 - p)n-1

Probability of 2 bits in error = nC2p2(1 - p)n-2

Thus, total probability= (1 - p)n

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 12

There are 60 students in a class. The students are divided into three groups A, B and C of 15, 20 and 25 students, respectively. The groups A and C are combined to form group D. What is the average weight of the students in group D?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 12
There is no indication of weights of the students in the question. Therefore, it is not possible to find the relation between the weights of students in groups A, B, C, and D.
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 13

Transfer function of an LTI system is given as G(S)= (s-1)/(s+1)

Find the gain of the system at a frequency of 1 rad/s.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 13

We have, putting s=jω G(jω)=

= 1

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 14

The probability that a man will live 10 more years is 1/4 and the probability that his wife will live 10 more years is 1/3. The probability that neither of them will be alive in 10 years is

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 14
Probability that a man will live 10 more years = 1/4

Probability that man will not live 10 more years = 1 - 1/4 = 3/4

Probability that his wife will live 10 more years = 1/3

Probability that his wife will not live 10 more years = 1 - 1/3 = 2/3

Then, probability that neither will be alive in 10 years = (3/4) x (2/3) = 1/2

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 15

Consider the Schmitt trigger circuit shown below the Hysteresis width in Volts is……?


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 15
Apply KCL at Va

When V0 = +VsatV2 = VUTP

When V0 = +VsatVa = VLTP

Here Vref = -10

R1 = 10k,

R2 = 50k,

R3 = 10k

VUTP =

= - 3.4545V

Similarly VLTP = -5.6363

So hyseresis width

= UTP - LTP

= (-3.4545) - (5.6363)

= 2.19V

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 16

Voting is the privilege for which wars have been fought, protests have been organized, and editorials have been written. "No taxation without representation," was a battle cry of the American Revolution. Women struggled for suffrage, as did many minorities. Eighteen year olds clamored for the right to vote, saying that if they were old enough to fight in the war, then they should be allowed to vote. Yet Americans have a deplorable voting history, and many will tell you that they have never voted.

Which of the following words is the best synonym for the word 'privilege' as used in the passage?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 16
The context mentions that wars have been fought for 'voting' and 'privilege' means 'a special right'.
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 17

A non-ideal diode is used in a clamper circuit. The forward and reverse resistances of the diode are 200 ohms and 250 kilo ohms, respectively. The circuit designer has designed the circuit using a 10 kilo ohm resistor. The value of resistor to be connected in parallel to correct the circuit would be approximately

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 17
We have a formula to get the value of resistor to be used in a clamper circuit and it is given by R =

This gives value of R as 7.07 kΩ.

Since 10 kΩ resistor is being used, to make effective resistance as 7.07 kΩ, a resistor of value 24.18 kΩ has to be connected in parallel.

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 18

Two trains start at the same time from two stations A and B towards each other.

They arrive at B and A respectively in 5 hours and 20 hours after they passed each other.

If the speed of the train that started from A is 56 kmph, then what is the speed of the second train (in kmph)?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 18
Let the speeds of two trains starting from station A and B be S1 and S2 respectively and the time taken by them after meeting be t1 and t2 respectively.

Then, we can use this equation to get the answer:

S2 = 28 kmph

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 19

If a characteristics equation has roots S = -3 ± J4 then the values of natural frequency and damping ratio will be respectively.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 19

We know that S =

Thus, option c is correct answer.

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 20

A man starts at a certain point, walks one km east, then two km north, one km east, one km north, one km east and finally one km north to arrive at the destination. What is the shortest distance (in km) from the starting point to the destination?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 20

Let us assume that man starts from point O and reaches his destination at point A.

The shortest distance between O and his destination is OA = = 5 km

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 21

Calculate value of RL so that maximum power is transmitted through RL Also calculate maximum power generated

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 21

To find RL

For maximum power transfer RL = RS

All voltage sources should be short circuited and current sources should be open circuited and RL should be removed.

Consider the figure:

RS = 5|| 10 = 50/15 =3.33 Ω

Therefore RL = 3.33 Ω

To calculate power generated:

R= 5 + 3.33||10 = 7.5 Ω

I=V/R =10/7.5 = 1.33 A

Iab= 1.33×10/(10+3.33) = 1A

P = I2 RL = (1.33)2 × 3.33 =5.8 W

Thus, option D is the correct answer.

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 22

If u = log , find the value of x .(Answer up to the nearest integer)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 22

On solving, we get

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 23

Find the transfer function for the given block diagram?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 23

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 24

If the closed-loop transfer function of a control system is given as T(s) = then it is

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 24
In a minimum phase system, all the poles as well as zeros are on the left half of the s-plane. In given system, as there is right half zero (s = 5), the system is a non-minimum phase system.
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 25

For the n-channel enhancement MOSFET shown in the given figure, Threshold voltage Vtn=2V,The drain current ID of the MOSFET is 4mA when drain resistance RD is 1kΩ, If value of RD is increase to 4kΩ, then drain current ID will become

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 25
ID=K(VGS-V(E(th)2

4mA=K(VGS-2)2

Here VGS=10-4×1=6

∴4=k(6-2)2

K= 4/16=¼

When RD is increased to 4kΩ.

VGS=10-4ID

Now ID= 4/16(10-4ID-2)2

Solving the above equation for ID we will get

ID =2.8 mA and ID =1.4 mA and

but ID can not be 2.8 mA as VGS becomes negative so,

ID =1.4 mA

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 26

The root locus of the system G(s) H(s) = has the break-away point located at

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 26

Since, breakpoint must lie on root locus. So, s = -0.784 is possible.

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 27

As it comes in the form of 0/0 so applying LH rule QUESTION IS DISPLACED

Putting t=1/4W

P (t) = = 0.5


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 27
fm=3.4kHz

fs=8kHz

Qs=64

⇒2n=64

⇒∩=no.of bits=6

m=10

Total bits in a frame =nm+5/2

(As extra bit is added after every alternate frame)

=6×10+2.5

=62.5bits

Bit rate, rb total bits in a frame × sampling frequency

=62.5×8000

=5×105bits/sec

∴Minimum channel bandwidth,

BW = rb/2 = 2.5 x 105

= 0.25 х 105

= 0.25 x MHz

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 28

A conducting circular loop of radius 20 cm lies in the z = 0 plane in a field B = 20 cos 377t az mWb/m2. The induced voltage in the loop is

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 28

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 29

The transfer function of a network can be written as

(1+s)/(1+0.5s) . The maximum phase angle occurs at a frequency of _______ rad/sec.


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 29
Comparing with standard transfer function

Here, τ=1

and aτ=0.5

or a=0.5

∵ α< />

∴ Lead network

The maximum phase occurs at a frequency of

ωm=

= 2rad/sec

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 30

If v = 2xy, then the analytic function f (z) = u + iv is

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 30

By Milne's Method, f'(z) = g(z,0) + ih(z,0) = 2z + i0 = 2z

On intergrating, f(z) = z2 + c

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 31

Consider the network shown in figure, find i(t) for t > 0.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 31

For t< />

The equivalent circuit is

The equivalent circuit is

Applying Laplace transform to the above circuit

By applying inverse Laplace transform

i(t) = -10e-4t A

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 32

A fast FH/MFSK system has the following parameters.

Number of bits per MFSK symbol = 4

Number of pops per MFSK symbol = 4

The processing gain (in dB) of the system is ____.(Answer up to the nearest integer)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 32
The processing gain is PG = 4 × 4 = 16

in decibels, PG = 10 log10 16 = 12 dB

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 33

In the figure shown below

the value of IIn will be

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 33
Since current through MOS (2) is 1 mA and thus

ID2 = 2 mA

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 34

In spherical coordinates, let denote unit vectors along the directions.

E = 100/r sin θ cos (wt –br) âθ V/M

H = 0.265/r sin θ cos (wt –br) âΦ V/M

represent the electric and magnetic field components of the EM wave at large distances r from a dipole antenna, in free space. The average power (W) crossing the hemispherical shell located at r = 1 km, 0≤ q≤ π /2 is ____(Answer up to one decimal place)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 34

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 35

Consider the 2 port circuit given below

Hybrid parameter h12 for the circuit is _____.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 35

Redrawing the circuit by keeping I1 = 0

V2=10(I2−Ix)

=4ix+6ix+10ix

10I2 = 30ix

I2 = 3ix

V1 = 10ix

V2 = 10 (|2 - 1x)

V2 = 201x

V1/V2 = 10ix/20ix = 0.5

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 36

A 0 to 6 counter consists of 3 flip flops and a combination circuit of 2 input gates. The combination circuit consists of

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 36
Counter must be reset when it counts 111. This can be implemented by the following circuitry

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 37

Two LTI systems in cascade form as shown in below figure-

If h1(n) = 3nu(n) and h2(n) = 3δ(n) – 3δ(n – 1) and If x(n) = sin(n) then output will be

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 37

Here two LTI systems are in cascaded form and the overall impulse response is-

h(n)=h2(n)*h1(n)=[ 3δ(n) – 3δ(n – 1)]* 3n u(n)

= 3n+1 u(n)- 3n+1 u(n-1)

= 3n+1 δ (n)

h(n)= 31 δ (n)

Since input is sin (n) hence output will be

h(n)*Sin (n)= 3δ (n)*sin(n)=3sin(n)

thus the band width gets reduced in a multi-stage amplifier.

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 38

What is addition of (- 64)10 and (80)16?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 38
Converting in decimal, we have

(80)16 = 8 × 16 = (128)10

(128)10 + (− 64)10 = (64)10

(64)10 = (01000000)2

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 39

Assuming that the opamp in the circuit shown below is ideal, the output voltage V0 (in volts) is______

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 39
This is a Non-inverting Op-amp.

But V+ is not equal to V-

So, Vo=A(V+ - V-)

Since this is an ideal op-amp. Gain is infinite.

But output voltage can't be infinite. It is equal to max. supply voltage i.e. 12V

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 40

For the circuit shown in figure, Thevenin's voltage and Thevenin's equivalent resistance at terminal ab is

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 40
Open circuit at terminal ab is shown below

Applying KCL at note we get

Short circuit at terminal ab is shown below

Short circuit current from terminal ab is

Here current source being is series with dependent voltage source make it ineffective.

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 41

The forward path transfer function of a unity feedback system is

G(s) = k/(sn(s+a))

The system has 10% overshoot and velocity error constant Kv = 100.

The value of K is

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 41

So ξ=0.6

K = 14400

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 42

An ideal pn junction diode is operating in the forward bias region. The change in diode voltage, that will cause current to increase by a factor of 10, is (Answer up to one decimal place)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 42

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 43

The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input „In‟ and an output ‘Out’. The initial state of the FSM is S0

If the input sequence is 10101101001101, starting with the left-most bit, then the number times ‘Out’ will be 1 is __________.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 43
From the state diagram, let us obtain the transition of states and out when IN channel.

Initial state is

So, the input sea is 10101101001101

When,

IN = 1 Then S0→S1= With out =0 IN=0 Then S1→Ss=W ith out =0

IN = 1 Then S1→Sn=With out =1

IN = 0 Then S3→S2=With out =0

IN = 1 Then S2→S3=With out =1

IN = 1 Then S3→S1= With out =0

IN=0 Then S1→S2=With out =0

IN=1 Then S2→S3=With out =1

IN=0 Then S3→S2=With out =0

IN=0 Then S2→Su= Without =0

IN=1 Then S0→S1=With out =0

IN=1 Then S1→S1= Without =0

IN=0 Then S1→S2=With out =0

IN=1 Then S2→S3=With out =1

→ The ticketed mark now corresponding to output =1.

So output will be 1′4′ times.

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 44

A digital system is required to amplify a binary-encoded audio signal. The user should be able to control the gain of the amplifier from a minimum to a maximum in 100 increments. The minimum number of bits required to encode, in straight binary, is

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 44
The minimum number of bits required to encode 100 increment is

Or

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 45

Consider the circuit shown in the figure below:

Let the forward voltage drop VΥ=0.6V for the diode. The circuit is connected with two power supplies with values V1 = 10 V and V2 = 15 V, then the value of current passing through the diode D is equal ______ mA.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 45
Assuming the diode to be considered as load, the the venin’s equivalent circuit can be drawn for diode D.

Thus, VTh1=6.66and RTh1=3.33kΩ

RTh2=10V and RTh2=6.66kΩ

∵ VTh2 >VTh1, Thus the diode will be forward biased hence the current will flow, hence the equivalent circuit is drawn as:

Thus, I= (10-0.6-6.66)/10×10-3

I = 0.2734mA

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 46

Consider the BJT circuit shown in the figure below.

For the circuit, the zener current Iz (in mA) will be (Answer up to two decimal places)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 46

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 47

A ternary channel emits 3 symbols x1, x2 and x3 with probabilities Px(x1) = 0.4 and Px(x2) = Px(x3) = Q. The mutual information I(x|y) (in bits/symbol) would be given as (p is given to be 0.8)

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 47
Probabilities P,Q and Q are 0.4,0.3 and 0.3

We know that mutual information is given as follows,

I(x ∣ y) = H(x) − H(x ∣ y)

And Entropies are defined as,

H(x) = ∑−P (xi) log2 ⁡P(xi)

We get Hx as 1.571 bits/symbol.

And,

H(x ∣ y)= ∑ij − P(yj) P(xi ∣ yj) log2 ⁡P(xi)

We get Hx|y as 0.4332 bits/symbol

Mutual Information would be obtained as,

1(x ∣ y)=1.571−0.4332

=1.1378bits/symbol

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 48

What is the minimum number of gates required to implement the Boolean function (AB + C) if we have to use only 2-input NOR gates? (Answer up to the nearest integer)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 48
AB + C = (A + C)(B + C) = ((A + C)' + (B + C)')'

So, '3' 2-input NOR gates are required.

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 49

Assuming that the Op-amp in the circuit shown is ideal, VO is given by

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 49
Virtual ground and KCL at inverting terminal gives

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 50

Consider the network shown below operating at room temperature:

The input impedance Z(Ω) of the circuit will be _____. (Answer up to one decimal place)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 50

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 51

An a stable multi vibrator circuit using IC 555 timer is shown below. Assume that the circuit is oscillating steadily

The voltage VC across the capacitor varies between

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 51
The Voltage Vc varies between 2Vcc/3 to Vcc/3 (because internally in 555 timer three 5k reistors are biased and drop across each one of them is vcc/3 )given that, Vcc=9V

therefore, voltage Vc varies between 3V and 6V.

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 52

A point charge of 2 × 10-16 C and 5 × 10-26 kg is moving in the combined fields B = - 3ux + 2uy - uz mT and E = 100 ux - 200 uy - 300 uz V/m. If the charge velocity at t = 0 is v (0) = (2ux - 3uy - 4uz) 105 m/s, the acceleration of charge at t = 0 is

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 52
V(0) × B = 2(ux – 3uy – 4uz) 105 × (-3ux + 2uy - uz) 10-3

= 1100ux + 1400uy – 500uz

F(0) = q[E + v × B]

= 2 × 10-16 [1200ux + 1200uy – 200uz]

= 4 × 10-14 [6ux + 6uy – uz]

= 800 [6ux + 6uy - uz] 109 m/s2

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 53

In the given circuit, the maximum power (in watts) that can be transferred to the load R, i


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 53

I Thevenin equivalent of the circuit will be

Therefore,

For maximum power

= 1.657W

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 54

For the circuit shown below, the resonant frequency f0 (in MHz) is ______. (Answer up to two decimal places)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 54

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 55

A cascade connection of two voltage amplifiers A1 and A2 is shown in the figure. The open-loop gain Av0, input resistance Rin, and output resistance RO for A1 and A2 are as follows:

A1 ∶ Av0 = 10, Rin = 10kΩ, R_0 = 1kΩ

A2 ∶ Av0 = 5, Rin = 5kΩ, R0 = 200Ω

The approximate overall voltage gain Vout /Vin is _________.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 55
Overall voltage gain;

AV = 34.722

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 56

Assume that all inputs in the open-collector TTL gate shown below are in the high state of 5 V.

The voltage (in V) at the base of transistor Q1 will be (Answer up to one decimal place)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 56
TTL is having the basic gate as a NAND.

In a NAND gate, if all the inputs are high, output is low.

So, transistors Q2 and Q3 conduct and saturate.

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 57

Consider an MOS structure with n-type silicon. A metal- semiconductor work function difference of Φms = - 0.35 V is required. For an aluminium- silicon dioxide junction, Φm′ = 3.20 V and for a silicon-silicon dioxide junction x′ = 3.25 V and Eg = 1.11 eV. If the gate is aluminium, then what is the silicon doping required to meet the specification?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 57
The metal-semiconductor work function difference is defined as

Φms = Φm′ - ( χ′ +Eg/2e - Φjn )

Substituting the given values;

- 0.35 = 3.20 – (3.25 + 0.56 - Φjn)

Φjn = 0.26 V

We may also express Φjn as

Φjn = Vt ln (Nd/ni)

So, 0.26 = 0.0259 ln

Nd = 3.43 ×1014 cm-3

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 58

For the transistor in circuit shown below, Is = 10-15 A, βF = 100,βR = 1. The current ICBO (in Å) is ____ × 10-15 (Answer up to two decimal places)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 58

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 59

A discrete memoryless source with source alphabet ∅={S0,S1,S2} and source statistics {0.7, 0.15, 0.15}Calculate the entropy of source and the entropy of second-order extension of the source.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 59
The entropy of the source is

= 0.3602+0.4105+0.4105

=1.181 bits

the entropy of second-order extension of the source is

H(S2)=2×1.181

=2.362 bits

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 60

A Y-network has resistances of 10 Ωeach in two of its arms, while the third arm has a resistance of 11Ω. In the equivalent -network, the lowest value (inΩ ) among the three resistances is ________.(Answer up to two decimal places)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 60
For the given problem, we sketch the Y-network as

For the given Y-network, we obtain the equivalent resistances of Δ-network as

= 32Ω

The lowest value among the three resistance is

RA = 29.09Ω

Note : Since, we have to determine lowest value, so the resistance should be determined only for the expression having maximum value in denominator. Thus the calculation of RB and RC are not required .

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 61

The electric field vector in spherical coordinates(r,θ,ϕ)is given by

The potential of point (r=2 m, θ = π/2, ϕ =0) with respect to (r=4 m,θ=π, θ=π)is given by

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 61

[Note:θ, ∅ Variations does not affectV

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 9 - Question 62

A periodic variable x is shown in the figure as a function of time. The root mean- square (rms) value of x is ________.(Answer up to four decimal places)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 62
We have the waveform of periodic variable x as shown below.

Form the waveform, we define variable x in the period T as

So, the rms value of x(t) is obtained as

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 63

Consider a HVDC link which uses thyristor based line-commutated converters as shown in the figure. For a power flow of 750 MW from System 1 to System 2, the voltages at the two ends and the current, are given by : V1 = 500 kV, V2 = 485 kV and I = 1.5 kA. If the direction of power flow is to be reversed (that is, from System 2 to System 1) without changing the electrical connections, then which one of the following combinations is feasible?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 63
To maintain the direction of power flow from system 2 to system 1 the voltage V1 = - 485 kV and voltage V2 = - 500 kV and I = 1.5 kA

Since, current cannot flow in reverse direction

Option (A) is the correct answer.

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 64

The solution of the differential equation x dy - y dx = dx is given by

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 64

GATE Mock Test Electronics Engineering (ECE)- 9 - Question 65

An LTI system having transfer function

and input x(t) = sin(t +1) is in steady state. The output is sampled at a rate ω rad/s to obtain the final output {y(k)}. Which of the following is true?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 9 - Question 65

= sin (t + 1)

⇒ w = 1

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