Test: Asynchronous & Synchronous DRAM


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20 Questions MCQ Test Computer Architecture & Organisation (CAO) | Test: Asynchronous & Synchronous DRAM

Test: Asynchronous & Synchronous DRAM for Computer Science Engineering (CSE) 2022 is part of Computer Architecture & Organisation (CAO) preparation. The Test: Asynchronous & Synchronous DRAM questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: Asynchronous & Synchronous DRAM MCQs are made for Computer Science Engineering (CSE) 2022 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Asynchronous & Synchronous DRAM below.
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Test: Asynchronous & Synchronous DRAM - Question 1

The Reason for the disregarding of the SRAM’s is ________

Detailed Solution for Test: Asynchronous & Synchronous DRAM - Question 1

Answer: c
Explanation: The reason for the high cost of the SRAM is because of the usage of more number of transistors.

Test: Asynchronous & Synchronous DRAM - Question 2

 The disadvantage of DRAM over SRAM is/are _______

Detailed Solution for Test: Asynchronous & Synchronous DRAM - Question 2

Answer: c
Explanation: This means that the cells wont hold their state indefinetly.

Test: Asynchronous & Synchronous DRAM - Question 3

The reason for the cells to lose their state over time is

Detailed Solution for Test: Asynchronous & Synchronous DRAM - Question 3

Answer: b
Explanation: Since capacitors are used the charge descipates over time.

Test: Asynchronous & Synchronous DRAM - Question 4

The capacitors lose the charge over time due to

Detailed Solution for Test: Asynchronous & Synchronous DRAM - Question 4

Answer: a
Explanation: The capacitor loses charge due to the backward current of the transistro and due to the small resistance.

Test: Asynchronous & Synchronous DRAM - Question 5

_________ circuit is used to restore the capacitor value.

Detailed Solution for Test: Asynchronous & Synchronous DRAM - Question 5

Answer: a
Explanation: The sense amplifier detects if the value is above or below the threshlod and then restores it.

Test: Asynchronous & Synchronous DRAM - Question 6

To reduce the number of external connections reqiured, we make use of ______

Detailed Solution for Test: Asynchronous & Synchronous DRAM - Question 6

Answer: b
Explanation: We multiplex the various address lines onto fewer pins.

Test: Asynchronous & Synchronous DRAM - Question 7

The processor must take into account the delay in accessing the memory location, such memories are called ______

Test: Asynchronous & Synchronous DRAM - Question 8

To get the row address of the required data ______ is enabled.

Detailed Solution for Test: Asynchronous & Synchronous DRAM - Question 8

Answer: b
Explanation: This makes the contents of the row required refreshed.

Test: Asynchronous & Synchronous DRAM - Question 9

 In order to read multiple bytes of a row at the same time, we make use of ______

Detailed Solution for Test: Asynchronous & Synchronous DRAM - Question 9

Answer: a
Explanation: The latch makes it easy to ready multiple bytes of data of the same row simulteneously by just giving the consecutive column address.

Test: Asynchronous & Synchronous DRAM - Question 10

The block transfer capability of the DRAM is called ________

Test: Asynchronous & Synchronous DRAM - Question 11

The difference between DRAM’s and SDRAM’s is/are ________

Detailed Solution for Test: Asynchronous & Synchronous DRAM - Question 11

Answer: d
Explanation: The SDRAM’s make use of clock signals to synchronise their operation.

Test: Asynchronous & Synchronous DRAM - Question 12

 The difference in address and data connection between DRAM’s and SDRAM’s is

Detailed Solution for Test: Asynchronous & Synchronous DRAM - Question 12

Answer: c
Explanation: The SDRAM uses buffered storage of address and data.

Test: Asynchronous & Synchronous DRAM - Question 13

A _______ is used to restore the contents of the cells.

Detailed Solution for Test: Asynchronous & Synchronous DRAM - Question 13

Answer: b
Explanation: The Counter helps to restore the charge on the capacitor

Test: Asynchronous & Synchronous DRAM - Question 14

The mode register is used to

Detailed Solution for Test: Asynchronous & Synchronous DRAM - Question 14

Answer: b
Explanation: The mode register is used to choose between burst mode or bit mode of operation.

Test: Asynchronous & Synchronous DRAM - Question 15

 In a SDRAM each row is refreshed every 64ms. 

Test: Asynchronous & Synchronous DRAM - Question 16

The time taken to transfer a word of data to or from the memory is called as ______

Detailed Solution for Test: Asynchronous & Synchronous DRAM - Question 16

Answer: c
Explanation: The performance of the memory is measured by means of latency.

Test: Asynchronous & Synchronous DRAM - Question 17

 In SDRAM’s buffers are used to store data that is read or written. 

Detailed Solution for Test: Asynchronous & Synchronous DRAM - Question 17

Answer: a
Explanation: In SDRAm’s all the bytes of data to be read or written are stored in the buffer until the operation is complete.

Test: Asynchronous & Synchronous DRAM - Question 18

The SDRAM performs operation on the _______

Detailed Solution for Test: Asynchronous & Synchronous DRAM - Question 18

Answer: a
Explanation: The SDRAM’s are edge-triggered.

Test: Asynchronous & Synchronous DRAM - Question 19

DDR SDRAM’s perform fster data transfer by

Detailed Solution for Test: Asynchronous & Synchronous DRAM - Question 19

Answer: b
Explanation: By transfering data on both the edges the bandwidth is effectively doubled.

Test: Asynchronous & Synchronous DRAM - Question 20

To improve the data retrieval rate

Detailed Solution for Test: Asynchronous & Synchronous DRAM - Question 20

Answer: a
Explanation: The division of memory into two banks makes it easy to access two different words at each edge of the clock.

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