A switching function of four variable, f (w, x y, z) is to equal the product of two other function f_{1} and f_{2}, of the same variable f = f_{1}f_{2} . The function f and f_{1} are as follows :
f = ∑m(4,7,15)
f = ∑m(0,1,2, 3, 4,7, 8,9,10,11,15)
Que: The number of full specified function, that will satisfy the given condition, is
f = ∑m(4,7,15)
f_{1} = ∑m(0,1,2, 3, 4,7, 8,9,10,11,15)
f_{2} = ∑m(4,7,15) + ∑dc(5, 6, 12, 13, 14)
There are 5 don't care condition. So 2^{5} = 32 different functions f_{2}
A switching function of four variable, f (w, x y, z) is to equal the product of two other function f_{1} and f_{2}, of the same variable f = f_{1}f_{2} . The function f and f_{1} are as follows :
f = ∑m(4,7,15)
f_{1} = ∑m(0,1,2, 3, 4,7, 8,9,10,11,15)
Que: The simplest function for f_{2} is
A fourvariable switching function has minterms m_{6 }and m_{9}. If the literals in these minterms are complemented, the corresponding minterm numbers are
The minimum function that can detect a “divisible by 3’’ 8421 BCD code digit (representation D_{8} D_{4} D_{2} D_{1} ) is given by
0, 3, 6 and 9 are divisible by 3
f =
For a binary half subtractor having two input A and B, the correct set of logical expressions for the outputs D = (A  B) and X (borrow) are
What type of logic circuit is represented by the figure shown below?
After solving the circuit we get (A’B’)+AB as output, which is XNOR operation. Thus, it will produce 1 when inputs are even number of 1s or all 0s, and produce 0 when input is odd number of 1s.
The building block shown in fig. is a active high output decoder.
Que: The output X is
The building block shown in fig. is a active high output decoder.
Que: The output Y is
A logic circuit consist of two 2 x 4 decoder as shown in fig.
The output of decoder are as follow
The value of f ( x, y, z) is
A MUX network is shown in fig.
Que : Z_{1} =?
The output of first MUX is
How many 3lineto8line decoders are required for a 1of32 decoder?
A MUX network is shown in fig.
Que: This circuit act as a
The equation of Z_{1} is the equation of sum of A and B with carry and equation of 2 is the resultant carry. Thus, it is a full adder.
The network shown in fig. implements
The MUX shown in fig. P4.2.31 is 4 * 1 multiplexer. The output Z is
Correct Answer : c
Explanation : Z = (bar AB)C + (bar A)B + (bar B)A + AB
= (bar A)[(barB)C + B) + A[(bar B) + B]
= (bar A)[(B + C)] + A
= A + B + C
The output of the 4 x 1 multiplexer shown in fig. is
The MUX shown in fig. is a 4 x 1 multiplexer. The output Z is
The output from the upper first level multiplexer is f_{a} and from the lower first level multiplexer is f_{b}
For the logic circuit shown in fig.the output Y is
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