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Test: Digital Electronics - 1 - Electrical Engineering (EE) MCQ


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25 Questions MCQ Test Digital Electronics - Test: Digital Electronics - 1

Test: Digital Electronics - 1 for Electrical Engineering (EE) 2024 is part of Digital Electronics preparation. The Test: Digital Electronics - 1 questions and answers have been prepared according to the Electrical Engineering (EE) exam syllabus.The Test: Digital Electronics - 1 MCQs are made for Electrical Engineering (EE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Digital Electronics - 1 below.
Solutions of Test: Digital Electronics - 1 questions in English are available as part of our Digital Electronics for Electrical Engineering (EE) & Test: Digital Electronics - 1 solutions in Hindi for Digital Electronics course. Download more important topics, notes, lectures and mock test series for Electrical Engineering (EE) Exam by signing up for free. Attempt Test: Digital Electronics - 1 | 25 questions in 25 minutes | Mock test for Electrical Engineering (EE) preparation | Free important questions MCQ to study Digital Electronics for Electrical Engineering (EE) Exam | Download free PDF with solutions
Test: Digital Electronics - 1 - Question 1

What is the direction of control bus?

Test: Digital Electronics - 1 - Question 2

In a certain digital waveform, the period is four times the pulse width. The duty cycle is ________.

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Test: Digital Electronics - 1 - Question 3

For the circuit shown below, Q = 0 initially. What shall be the subsequent states of Q when clock pulses are given?

Detailed Solution for Test: Digital Electronics - 1 - Question 3

The given circuit
Given that initially flip-flop is cleared i.e., Q = 0. After applying the CLK pulses, we get 1, 0, 1, 0......
Correct option is A. 

Test: Digital Electronics - 1 - Question 4

Which of the following operation are performed on linear queues?

  1. Testing a linear queue for underflow
  2. Enqueue operation
  3. Dequeue operation
  4. Testing a linear queue for overflow.
Select the correct answer using the codes given below the lists
Test: Digital Electronics - 1 - Question 5

If Vin is 0.99 V, what is the digital output of the ADC0801 after INTER goes low?

Test: Digital Electronics - 1 - Question 6

As access time is decreased, the cost of memory

Test: Digital Electronics - 1 - Question 7

Assertion (A): Hamming code is commonly used for error correction

Reason (R): In Hamming code the number of parity bits increases as the number of information bits increases.

Test: Digital Electronics - 1 - Question 8

A 2 bit binary multiplier can be implemented using

Test: Digital Electronics - 1 - Question 9

A microcomputer has memory locations from 0000 to FFFF, each storing 1 byte. How many bytes can be the memory store?

Test: Digital Electronics - 1 - Question 10

Typical size of digital IC is about

Test: Digital Electronics - 1 - Question 11

A clock signal coordinates the working of different flip flops.

Test: Digital Electronics - 1 - Question 12

In 8085, usually the vector location and the next two memory location contain a JMP instruction. This allows the programs to branch to

Test: Digital Electronics - 1 - Question 13

In which of these does thermionic emission occur?

Test: Digital Electronics - 1 - Question 14

In a positive-edge-triggered JK flip-flop, a low J and a low K produce __________ state. A high __________ on the rising edge of the clock.

Test: Digital Electronics - 1 - Question 15

The rate of change of digital signals between High and Low level is

Test: Digital Electronics - 1 - Question 16

Find the decimal value of 111001:

Test: Digital Electronics - 1 - Question 17

Which of the following is best suited for parity checking and parity generation?

Test: Digital Electronics - 1 - Question 18

In the circuit shown below, the outputs Y1 and Y2 for the given initial condition Y1 = Y2 = 1 and after four input pulses will be

Test: Digital Electronics - 1 - Question 19

The op amp is used in

Test: Digital Electronics - 1 - Question 20

Assertion (A): Power drain of CMOS increases with operating frequency

Reason (R): All unused CMOS inputs should be tied either to a fixed voltage level (0 or VDD) or to another input.

Test: Digital Electronics - 1 - Question 21

For the logic circuit of the given figure the simplified Boolean expression is

Test: Digital Electronics - 1 - Question 22

In two level logic, logic race does not occur.

Test: Digital Electronics - 1 - Question 23

A digital clock uses __________ chip

Test: Digital Electronics - 1 - Question 24

Which of the following conversion is incorrect?

Test: Digital Electronics - 1 - Question 25

The contents of stack location 2109 H after the call operation will be

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