In the circuit sho
Q_{o} = Q_{1} = 0 Then the values of QO and QI after 335^{th} clock pulse are _____________
An R — 2R ladder type DAC is shown in Figure if a switch status is '0', then 0 volt is applied and If a switch status is '1' then 5 volt is applied to the corresponding terminal of DAC.
What is value of output voltage V_{0} for switch status s_{o} = 0, s_{1}= 1, s_{2} = 1.
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An R — 2R ladder type DAC is shown in Figure if a switch status is '0', then 0 volt is applied and If a switch status is '1' then 5 volt is applied to the corresponding terminal of DAC.
Q. What is the step size of DAC.
For the given circuit shown in figure signal generated at the output of AND gat is Y. there clock has signal frequency of 4 kHz, with duty cycle 50%
Q. What is the value of frequency of output Y
For a Flipflop formed from 2 NAND gates as shown in figure, the unusable state corresponds to
In the figure as long as XI = 1 and X2 = 1 the output Q remains at
The Minimum no. of 2 inputs NAND gate required to implement Boolean function f(A, B, C, D) =
ABCD are_______
The 4 variable function f is given in terms of min term as f(A, B, C, D) = E(2,3,8,10,11,12,14,15)
Q. If by use of KMap function is minimized in sum of product forms then SOP is
The 4 variable function f is given in terms of min term as f(A, B, C, D) = E(2,3,8,10,11,12,14,15)
Q. Above Minimised SOP, can be implemented by how many min^{m} no. of 2 input NAND gate.
Consider the following data in respect of a certain digital gate
l_{oH} = 0.2 mA I_{1H}= 40μ.A, 10_{L} = 16 mA, l_{iL} = 1.6 mA symbols have their meaning. Fan out will be
If x, y and z are three Boolean variables, then F(x,y,z) = x + xy + y + yz + z + xz is equivalent to
How many AND gates are required for a 1to8 multiplexer?
In a dual slope ADC if reference voltage is 100 mV and the first integration period is set as 50 msec.
For an input voltage of 120 mV, the second integration (deintegration) period is___ ms
In a dual slope type digital voltmeter, an unknown signal voltage is integrated our 100 cycles of clock. If the signal has a 50 Hz pick up the maximum clock frequency can be__ kHz
In circuit given if both Transistors have same VT what is the approximate value of highest possible output voltage vout if v_{h}, can range from 0 to V_{DD}, it is assumed that 0 < v_{T} < V_{DD}
In the I.C. logic gate shown in figure.
If threshold voltage V_{BE} is o.75 volt and V_{CE} _{(sat)} = 0.2 V, calculate. Value of output voltage
Q. If VA = VB = 4.5 volt
24 docs263 tests

24 docs263 tests
