Test: Digital Electronics- 2
20 Questions MCQ Test GATE Electrical Engineering (EE) 2023 Mock Test Series | Test: Digital Electronics- 2
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In the circuit sho
Qo = Q1 = 0 Then the values of QO and QI after 335th clock pulse are _____________
It is a MOD - 4 counter, because Johnson counter =
An R — 2R ladder type DAC is shown in Figure if a switch status is '0', then 0 volt is applied and If a switch status is '1' then 5 volt is applied to the corresponding terminal of DAC.
What is value of output voltage V0 for switch status so = 0, s1= 1, s2 = 1.
An R — 2R ladder type DAC is shown in Figure if a switch status is '0', then 0 volt is applied and If a switch status is '1' then 5 volt is applied to the corresponding terminal of DAC.
Q. What is the step size of DAC.
Step size
For the given circuit shown in figure signal generated at the output of AND gat is Y. there clock has signal frequency of 4 kHz, with duty cycle 50%
Q. What is the value of frequency of output Y
A FF is simply MOD-2 counter.
Just Solve by K-Map.
For a Flip-flop formed from 2 NAND gates as shown in figure, the unusable state corresponds to
when both X = Y = 0 then value of Q & 
will remain same so unstable.
In the figure as long as XI = 1 and X2 = 1 the output Q remains at
Let X1 = 1 & X2= 1
IfQ=0 & X1=1
The o/P of gate -2, will be 1, and which will make Q = 1
if Q = 1 & X2 = 1, then 0/P of gate - 2 will be 0 and which will make output of gate - 1 Q = 0
The Minimum no. of 2 inputs NAND gate required to implement Boolean function f(A, B, C, D) =
ABCD are_______
Correct Answer :- 3
Explanation :
The 4 variable function f is given in terms of min term as f(A, B, C, D) = E(2,3,8,10,11,12,14,15)
Q. If by use of K-Map function is minimized in sum of product forms then SOP is
The 4 variable function f is given in terms of min term as f(A, B, C, D) = E(2,3,8,10,11,12,14,15)
Q. Above Minimised SOP, can be implemented by how many minm no. of 2 input NAND gate.
Consider the following data in respect of a certain digital gate
loH = 0.2 mA I1H= 40μ.A, 10L = 16 mA, liL = 1.6 mA symbols have their meaning. Fan out will be
F.0 = 
= 5
Smalls of both will be Fan out
F.I = 
=10
If x, y and z are three Boolean variables, then F(x,y,z) = x + xy + y + yz + z + xz is equivalent to
How many AND gates are required for a 1-to-8 multiplexer?
The number of AND gates required will be equal to the number of outputs in a demultiplexer.
In a dual slope ADC if reference voltage is 100 mV and the first integration period is set as 50 msec.
For an input voltage of 120 mV, the second integration (de-integration) period is___ ms
t = 60 m sec
In a dual slope type digital voltmeter, an unknown signal voltage is integrated our 100 cycles of clock. If the signal has a 50 Hz pick up the maximum clock frequency can be__ kHz
50 x 100
In circuit given if both Transistors have same VT what is the approximate value of highest possible output voltage vout if vh, can range from 0 to VDD, it is assumed that 0 < vT < VDD
In the I.C. logic gate shown in figure.
If threshold voltage VBE is o.75 volt and VCE (sat) = 0.2 V, calculate. Value of output voltage
Q. If VA = VB = 4.5 volt
It is A NAND gate and if VA= VB = 4.5
Then o/p will be logic zero, as both are logic high
SO V0 = VCE, sat = 0•2v
if VA = 4.5v & VB = 0.2 v
so o/p will be 1, ie. Vo = 5 volt
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22 docs|274 tests
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22 docs|274 tests
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