Test: Electronic Devices - 5 - Electronics and Communication Engineering (ECE) MCQ

• As V_i is increased voltage drop across R_L increases and V₀ decreases.
• The sharpness of the transition region increases with the increasing load resistance.
• Hence R₃ > R₂ > R₁.

The doping density is given by:

= 10¹⁰ e^{(0.437/0.026)}

= 1.99 × 10¹⁷

• Flat band voltage is the voltage where there is no charge present in oxide or oxide-semiconductor interface. i.e. No thickness of channel
• C_ox is constant and decreased subsequently
  Note: Here, V_G is negative (for PMOS)
• Hence, voltage is decreased from positive (V_FB) to negative.

The insulator capacitance is the capacitance under strong accumulation

= 3.453 × 10^-7 F/cm²

Given, t_ox = 10 nm, d = 100 nm

C_min = series combination of C_ox and C_dep

= 0.09 ϵA

I_D-n = I_D-p

μ_n W_n = μ_p W_p

2 = (V_GS - 1)^2‑
V_GS = √2 + 1 = 2.414 V

To function as a current source, the transistor must be in saturation or V_DS > V_DS (sat).

V_DS (sat) = V_GS - V_TN

= 2.414 – 1

= 1.414.

Hence compliance voltage = 1.414 V.
Compliance voltage is the minimum voltage required to achieve the desired performance.

The small signal model with a test voltage V_x is shown.

The output resistance is given by:
 

From the circuit, V_gs = V_x

Applying KCL:

Given gate plate area, which is also MOS capacitor area A = 0.5 × 10^-2cm²

Oxide layer thickness t_ox = 80 nm

The value of MOS capacitance:
 

= 0.22 μF

Dielectric breakdown happens of field  greater than dielectric strength (5 × 10⁶ V/cm)

V = 5 × 10⁸ × 80 × 10^-9 V = 40V

Gate is connected to drain Both Transistor are in Saturation.

For M₁ Transistor:

⇒ (V - 8)² = 4
⇒ V - 8 = ± 2

(i) Taking +ve, V = 8 + 2 = 10 V (Not Possible)
(ii) Taking -ve, V = 8 - 2 = 6 V