Test: Features of Intel - Computer Science Engineering (CSE) MCQ

Explanation: The instruction can execute in a single cycle which is done by pipelining the instruction flow. The address calculations are performed as the instruction proceeds down the line. Pipelining may take several cycles, an instruction can potentially be started and completed on every clock edge, thus achieving the single cycle performance.

Explanation: In order to have instruction and data to the pipeline, the 80486 has an internal unified cache to contain both data and instructions. This helps in the independency of the processor on external memory.

Explanation: The instruction set is same as that of 80386 but there are some additional instructions available when the processor is in protected mode.

Explanation: The 80386 has two external interrupt signals which allow external devices to interrupt the processor. The INTR input creates a maskable interrupt while the NMI creates a non-maskable interrupt.

Explanation: While an interrupt cycle is running, the processor possesses two interrupts acknowledge bus cycles and reads an 8-bit vector number. This vector is then used to locate, within the vector table and it has the address of the corresponding interrupt service routine. NMI is automatically assigned as vector number 2.

Explanation: The 80386 can run in three different modes: the real mode, the protected mode, and a virtual mode. In real mode, the size of each segment is limited to 64 Kbytes and in protected mode, the largest segment size is increased to 4 Gbytes and the virtual mode is a special version of the protected mode.

Explanation: The 32-bit flag register possesses the normal carry zero, auxiliary carry, parity, sign and overflow flags.

Explanation: Derivative of the 80386DX called the 80386SX which provides the same architecture and lowers cost. To minimal the cost value, it uses an external 16-bit data bus and a 24-bit memory bus.

Explanation: Intel has 80386SL as the portable PCs which helps in controlling power and increases the power efficiency of the processor.

Explanation: 80486 have a five stage pipeline ALU. These include fetch, decode, execute, memory access and write back. This helps in accessing instruction faster and thus makes the processor faster. 80386DX have a three-stage pipelining which only includes fetch, decode and execute.

Explanation: Intel Pentium have many advanced features one of which is, it can execute two instructions per cycle thus improving the speed of the processor whereas 80486, 80386 and 80386DX does not have this feature.

Explanation: The intel Pentium possess two five-stage pipelines which allow the execution of two integer instruction jointly.

Explanation: The control register and system management mode register has first appeared in 80386SL and later on succeeded by other processors. These registers can provide intelligent power control.

Explanation: Intel Pentium is succeeded by Pentium pro. P1, P2, and P5 are the other processors of Intel.

Explanation: A branch instruction can change the program flow and multiple branch prediction allows the continuous execution of instructions based on assumptions. This can eliminate delay and thus speeds up the execution.