Test: Flip Flops - Electronics and Communication Engineering (ECE) MCQ

Latch is a type of bistable multivibrator having two stable states. Both inputs of a latch are directly connected to the other’s output. Such types of structure is called cross coupling and due to which latches remain in the latched condition.

The SR flip-flop actually has three inputs, Set, Reset and its current state. The Invalid or Undefined State occurs at both S and R being at 1.

In sequential circuits, the output signals are fed back to the input side. So, The circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called sequential circuits. Unlike sequential circuits, if output depends only on the present state, then it’s known as combinational circuits.

There are two type of sequential circuits viz., (i) synchronous or clocked and (ii) asynchronous or unclocked. Synchronous Sequential Circuits are triggered in the presence of a clock signal, whereas, Asynchronous Sequential Circuits function in the absence of a clock signal.

The basic latch consists of two inverters. It is in the sense that if the output Q = 0 then the second output Q’ = 1 and vice versa.

The output of latches will remain in set/reset untill the trigger pulse is given to change the state.

The cross-coupled connections from the output of one gate to the input of the other gate constitute a feedback path. For this reason, the circuits of NOR based S-R latch classified as asynchronous sequential circuits. Moreover, they are referred to as asynchronous because they function in the absence of a clock pulse.

The SR flip-flop is very effective in removing the effects of switch bounce, which is the unwanted noise caused during the switching of electronic devices.

The JK Flip Flop is the most widely used flip flop. It is considered to be a universal flip-flop circuit.

Therefore, the correct answer is C.

The basic S-R flip-flop can be constructed by cross coupling of NOR or NAND gates. Cross coupling means the output of second gate is fed to the input of first gate and vice-versa.

The sequential circuit is also called a latch because both are a memory cell, which are capable of storing one bit of information.

In S-R flip-flop, if Q = 0 the output is said to be reset and set for Q = 1.

• A flip-flop is a basic digital memory circuit, also known as a bistable multivibrator.
• It has two stable states, which can be used to store binary information.
• Each flip-flop can store exactly one bit of data, representing either a 0 or a 1.
• Flip-flops are fundamental building blocks of digital electronics systems used in computers, communications, and many other types of systems.`

Race around condition:

For JK flip-flop if J, K, and Clock are equal to 1 the state of flip-flop keeps on toggling which leads to uncertainty in determining the output of the flip-flop. This problem is called Race around the condition.

This can be eliminated by using the following methods.

• Increasing the delay of flip-flop
• Use of edge-triggered flip-flop
• Use of master-slave JK flip flop

The Master-slave configuration is used in a flipflop to eliminate the race around condition but not to store two bits of information.

The PRESET and CLEAR inputs of the JK Flip-Flop are asynchronous, which means that they will have an immediate effect on the Q and Q’ outputs regardless of the state of the clock and / or the J and K inputs.

1.When the preset input is activated, the flip-flop will be set (Q=1, not-Q=0) regardless of any of the synchronous inputs or the clock.

2.When the clear input is activated, the flip-flop will be reset (Q=0, not-Q=1), regardless of any of the synchronous inputs or the clock.

3.When preset and clear inputs are activated we get an invalid state on the output, where Q and not-Q go to the same state.

Important Points-
JK Flip-Flop Truth Table- From  truth table it can be seen that the CLEAR (CLR) and PRESET inputs are active at a low logic level  and put on the Q output of the Flip-Flop, a high logic level regardless of the state of the clock and / or the state of the J and K inputs.