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Computer Science Engineering (CSE) Exam  >  Computer Science Engineering (CSE) Tests  >  Computer Architecture & Organisation (CAO)  >  Test: Parallel & Serial Port - Computer Science Engineering (CSE) MCQ

Test: Parallel & Serial Port - Computer Science Engineering (CSE) MCQ


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20 Questions MCQ Test Computer Architecture & Organisation (CAO) - Test: Parallel & Serial Port

Test: Parallel & Serial Port for Computer Science Engineering (CSE) 2024 is part of Computer Architecture & Organisation (CAO) preparation. The Test: Parallel & Serial Port questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: Parallel & Serial Port MCQs are made for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Parallel & Serial Port below.
Solutions of Test: Parallel & Serial Port questions in English are available as part of our Computer Architecture & Organisation (CAO) for Computer Science Engineering (CSE) & Test: Parallel & Serial Port solutions in Hindi for Computer Architecture & Organisation (CAO) course. Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free. Attempt Test: Parallel & Serial Port | 20 questions in 20 minutes | Mock test for Computer Science Engineering (CSE) preparation | Free important questions MCQ to study Computer Architecture & Organisation (CAO) for Computer Science Engineering (CSE) Exam | Download free PDF with solutions
Test: Parallel & Serial Port - Question 1
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The _____ circuit enables the generation of the ASCII code when the key is pressed.

Detailed Solution for Test: Parallel & Serial Port - Question 1

Answer: c
Explanation: The signal generated upon the pressing of a button is encoded by the encoder circuit into the corresponding ASCII value.

Test: Parallel & Serial Port - Question 2
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To overcome multiple signals being generated upon a single press of the button, we make use of ______

Detailed Solution for Test: Parallel & Serial Port - Question 2

Answer: b
Explanation: When the button is pressed,the contact surfaces bounce and hence it might lead to generation of multiple signals.In order to overcome this we use Debouncing circuits.

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Test: Parallel & Serial Port - Question 3
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The best mode of conncetion between devices which need to send or recieve large amounts of data over a short distance is _____

Detailed Solution for Test: Parallel & Serial Port - Question 3

Answer: c
Explanation: The parallel port transfers around 8 to 16 bits of data simultaneously over the lines, hence increasing transfer rates.

Test: Parallel & Serial Port - Question 4
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The output of the encoder circuit is/are ______
Detailed Solution for Test: Parallel & Serial Port - Question 4

Answer: b
Explanation: The encoder outputs the ASCII value along with the valid signal which indicates that a key was pressed.

Test: Parallel & Serial Port - Question 5
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 The disadvantage of using parallel mode of communication is ______
Detailed Solution for Test: Parallel & Serial Port - Question 5

Answer: a
Explanation: The parallel mode of data transfer is costly as it involves data being sent over parallel lines.

Test: Parallel & Serial Port - Question 6
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In a 32 bit processor, the A0 bit of the address line is connected to _____ of the parallel port interface.
Test: Parallel & Serial Port - Question 7
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 The Status flag circuit is implemented using _____
Detailed Solution for Test: Parallel & Serial Port - Question 7

Answer: b
Explanation: The circuit is implemented using the edge triggered D flip flop, that is triggered on the rising edge of the valid signal.

Test: Parallel & Serial Port - Question 8
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 In the output interface of the parallel port, along with the valid signal ______ is also sent.
Detailed Solution for Test: Parallel & Serial Port - Question 8

Answer: b
Explanation: The idle signal is used to check if the device is idle and ready to receive data.

Test: Parallel & Serial Port - Question 9
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DDR stands for __________
Detailed Solution for Test: Parallel & Serial Port - Question 9

Answer: a
Explanation: This register is used to control the flow of data from the DATAOUT register.

Test: Parallel & Serial Port - Question 10
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 In a general 8-bit parallel interface, the INTR line is connected to _______
Test: Parallel & Serial Port - Question 11
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 The mode of transmission of data, where one bit is sent for each clock cycle is ______
Detailed Solution for Test: Parallel & Serial Port - Question 11

Answer: d
Explanation: In isochronous mode of transmission, each bit of the data is sent per each cycle.

Test: Parallel & Serial Port - Question 12
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The transformation between the Parallel and serial ports is done with the help of ______
Detailed Solution for Test: Parallel & Serial Port - Question 12

Answer: c
Explanation: The Shift registers are used to output the data in a desired format based on the need.

Test: Parallel & Serial Port - Question 13
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 The serial port is used to connect basically _____ and processor.
Detailed Solution for Test: Parallel & Serial Port - Question 13

Answer: a
Explanation: The serial port is used to connect keyboard and other devices which input or output one bit at a time.

Test: Parallel & Serial Port - Question 14
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The double buffer is used for
Detailed Solution for Test: Parallel & Serial Port - Question 14

- Double Buffering is a technique used in computing to enhance efficiency in handling data.
- It primarily involves two buffers that alternate between filling with new data and processing or displaying existing data.
- This method allows for the seamless and continuous processing of data, essential in applications like video playback or graphics rendering.
- The correct answer A: "Enabling receival of multiple bits of input" reflects the ability of double buffering to manage incoming data efficiently without delay or data loss.

Test: Parallel & Serial Port - Question 15
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______ to increase the flexibility of the serial ports.
Detailed Solution for Test: Parallel & Serial Port - Question 15

Answer: b
Explanation: The ports are made more flexible by enabling the input or output of different clock signals for different devices.

Test: Parallel & Serial Port - Question 16
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 UART stands for ________
Detailed Solution for Test: Parallel & Serial Port - Question 16

Answer: c
Explanation: The UART is a standard developed for designing serial ports.

Test: Parallel & Serial Port - Question 17
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The key feature of UART is
Test: Parallel & Serial Port - Question 18
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The data transfer in UART is done in ______
Detailed Solution for Test: Parallel & Serial Port - Question 18

Answer: a
Explanation: This basically means that the data transfer is done in asynchronous mode.

Test: Parallel & Serial Port - Question 19
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The standard used in serial ports to facilitate communication is _____
Detailed Solution for Test: Parallel & Serial Port - Question 19

Answer: c
Explanation: This is a standard which acts as a protocol for message communication involving serial ports.

Test: Parallel & Serial Port - Question 20
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In serial port interface, the INTR line is connected to _____
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Important Questions for Parallel & Serial Port

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Parallel & Serial Port MCQs with Answers

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