Test: RISC Exceptions


20 Questions MCQ Test Embedded Systems (Web) | Test: RISC Exceptions


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QUESTION: 1

What does MSR stand for?

Solution:

Explanation: The MSR is a machine state register. When the exception is recognised, the address of the instruction and the MSR are stored in the supervisor registers while handling an exception.

QUESTION: 2

 How many supervisor registers are associated with the exception mode?

Solution:

Explanation: When the exception is recognised, the address of the instruction and the machine state register(MSR) are stored in the supervisor registers in the exception mode. There are two supervisor registers SRR0 and SRR1.

QUESTION: 3

What happens when an exception is completed?

Solution:

Explanation: When an exception is recognised, the address of the instruction and the MSR are stored in the supervisor registers and the processor moves to the supervisor mode and starts to execute the handler which is associated with the vector table. The handler examines the DSISR and FPSCR registers and carries out the required function. When it gets completed the RFI or return-from-interrupt instruction is executed.

QUESTION: 4

How many general types of exceptions are there?

Solution:

Explanation: There are four general types of exceptions. They are synchronous precise, asynchronous precise, synchronous imprecise and asynchronous imprecise.

QUESTION: 5

 In which of the exceptions does the external event causes the exception?

Solution:

Explanation: The asynchronous exception is the one in which an external event causes an exception and is independent of the instruction flow. On the other hand, the synchronous exceptions are synchronised, that is, it is caused by the instruction flow.

QUESTION: 6

Which of the exceptions are usually a catastrophic failure?

Solution:

Explanation: An imprecise exception is a catastrophic failure in which the processor cannot continue processing or allow a particular task or program to continue.

QUESTION: 7

 Which of the exceptions allows the system reset or memory fault?

Solution:

Explanation: The system reset or memory fault falls into the category of imprecise exceptions while accessing the vector table.

QUESTION: 8

Which registers are used to determine the completion status?

Solution:

Explanation: The completion status can be determined by the information bits in the DSISR and FPSCR registers.

QUESTION: 9

 Which of the following does not support PowerPC architecture?

Solution:

Explanation: The synchronous imprecise is usually not supported on the PowerPC architecture and also in the MPC601, MPC603 etc.

QUESTION: 10

Which exceptions are used in the PowerPC for floating point?

Solution:

Explanation: . The PowerPC can handle the floating point exception by making use of the synchronous imprecise mode.

QUESTION: 11

Which exception is used in the external interrupts and decrementer-caused exceptions?

Solution:

Explanation: The asynchronous precise type exception is used to handle the external interrupts and decrementer-caused exceptions. Both these can occur at any time within the instruction flow.

QUESTION: 12

Which of the following can be done to ensure that all interrupts are recognised?

Solution:

Explanation: The exception handler performs some kind of handshaking to ensure that all the interrupts are recognised.

QUESTION: 13

How many types of exceptions are associated with the asynchronous imprecise?

Solution:

Explanation: Two types of exceptions are associated with the asynchronous imprecise. These are system reset and machine checks.

QUESTION: 14

 How is the internal registers and memories are reset?

Solution:

Explanation: By doing the system reset, all the current processing are stopped and the internal registers and the memories are reset.

QUESTION: 15

 How is the machine check exception is taken in an asynchronous imprecise?

Solution:

Explanation: The machine check exception is taken only if the ME bit of the MSR is set. If it is cleared, the processor will enter into a check stop state.

QUESTION: 16

 Which of the following are the exceptions associated with the asynchronous imprecise?

Solution:

Explanation: The machine check and the system reset are two types of exceptions which are associated with the asynchronous imprecise.

QUESTION: 17

 Which of the following possesses an additional priority?

Solution:

Explanation: The synchronous precise exceptions provide additional priority because it is possible for an instruction to generate more than one exception.

QUESTION: 18

Which of the following has more priority?

Solution:

Explanation: The system reset has the first priority then comes the machine reset, next priority moves for the instruction dependent, and the next priority is external interrupt, and last priority level goes for the decrementer interrupt.

QUESTION: 19

Which bit controls the external interrupts and the decrementer exceptions?

Solution:

Explanation: The EE bit in the MSR controls the external interrupts and the decrementer exceptions.

QUESTION: 20

Which bit controls the machine check exceptions?

Solution:

Explanation: The ME bit in the MSR controls the machine check interrupts.

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