Test: Semiconductor Memory Interfacing - Computer Science Engineering (CSE) MCQ

The semiconductor memories are organised as two dimension of array which consists of rows and columns.

The bits in a selected location are accessible using data bus.

 For n memory locations, log n(to the base of 2) address lines are required. For addressing 4K bytes of memory, 12 address lines are required since log(4KB) =log(4*1024)=log(2¹²)=12.

Since for n address lines, the number of memory locations able to address is 2^n.

In static memory, the upper 8-bit bank is called odd address memory bank.

In static memory, the lower 8-bit bank is called even address memory bank.

 In general, linear decoding is used to minimise the required hardware.

The two 4K*8 chips of RAM and ROM are arranged in parallel.

If Ao=0 then address is even and is in RAM. If Ao=1 then, address is odd and is in RAM.

 If at a time Ao and BHE(active low) both are zero, then both RAM and ROM are selected.