Test: Semiconductor Memory Interfacing
10 Questions MCQ Test | Test: Semiconductor Memory Interfacing
| 1 Crore+ students have signed up on EduRev. Have you? |
The semiconductor memories are organised as __________ dimension(s) of array of memory locations.
The semiconductor memories are organised as two dimension of array which consists of rows and columns.
If a location is selected, then all the bits in it are accessible using a group of conductors called
The bits in a selected location are accessible using data bus.
To address a memory location out of N memory locations, the number of address lines required is
For n memory locations, log n(to the base of 2) address lines are required. For addressing 4K bytes of memory, 12 address lines are required since log(4KB) =log(4*1024)=log(212)=12.
If the microprocessor has 10 address lines, then the number of memory locations it is able to address is
Since for n address lines, the number of memory locations able to address is 2^n.
In static memory, the upper 8-bit bank of available 16-bit memory chip is called
In static memory, the upper 8-bit bank is called odd address memory bank.
In static memory, the lower 8-bit bank of available 16-bit memory chip is called
In static memory, the lower 8-bit bank is called even address memory bank.
In most of the cases, the method used for decoding that may be used to minimise the required hardware is
In general, linear decoding is used to minimise the required hardware.
To obtain 16-bit data bus width, the two 4K*8 chips of RAM and ROM are arranged in
The two 4K*8 chips of RAM and ROM are arranged in parallel.
If (address line) Ao=0 then, the status of address and memory are
If Ao=0 then address is even and is in RAM. If Ao=1 then, address is odd and is in RAM.
If at a time Ao and BHE(active low) both are zero then, the chip(s) selected will be
If at a time Ao and BHE(active low) both are zero, then both RAM and ROM are selected.
|
Use Code STAYHOME200 and get INR 200 additional OFF
|
Use Coupon Code |
Download free EduRev App
Related content with Test: Semiconductor Memory Interfacing
|
|
|
|
Related tests with Test: Semiconductor Memory Interfacing
|
|
|
|
|
|
© EduRev
|
Education Revolution
|
Follow Us
|
