Test: Sequential Circuit - Electrical Engineering (EE) MCQ

Concept:

D-flipflop is a flipflop that produces a delay of exactly one cycle to the CLK.

The characteristic equation of a D flip flop is:

Q_n+1 = D

It is also known as ‘’Transparent latch” because Q_n+1 = D

Application:

From given sequential circuit:

Now,

So, counts state (Q₁ Q₀) follows the sequence:

00 → 01 → 10 → 00 → 01 ….

Ring counter:

The Ring shift counter is a recirculating register in which the serial output is connected back to the serial input as shown:

A Straight ring counter with ‘n’ flip-flops will have n states.

Johnson counter:

A Johnson counter is a modified ring counter, where the inverted output from the last flip flop is connected to the input to the first.

It is also called a twisted ring counter.

The MOD of the Johnson counter is 2n if n flip-flops are used.

The circuit diagram for a 4-bit Johnson Counter is as shown:

Latches and Flip-Flop:

• Latches and flip-flops are the basic elements to store 1-bit of data. Hence they are also known as a one-bit memory element.
• Latches change the output continuously when there is a change in the input, i.e. they are level triggered.
• Flip-flop is a combination of latch and clock. It changes the output that is adjusted by the clock.
• The main difference between a latch and a flip-flop is that a flip-flop has a clock signal, whereas a latch does not.
• We can say that a flip-flop without a clock is a latch.
• Latches are asynchronous, which means that the output of a latch depends on its input.
• Basically, there are 4 types of latches: SR latch, JK latch, D latch, T latch.

Concept:

If we pass the input signal to a single T-flip flop, we will get half of the frequency at the output.

Similarly, when we pass the input signal into a divide by M bit counter, the output frequency (f_out) will be:

Calculation:

Given is a mod-1024 ripple counter which means that it can count 1024 states.

To count 1024 number of flipflop required is:

1024 = 2ⁿ

n = 10 flip-flops

t_pdff = Propagation delay of flip flops

tpdff = 10^-6 sec.

Propagation delay per flipflop = 

= 10⁻⁶/10

= 100 nsec

A sequence detector is a sequential circuit that outputs 1 when a particular pattern of bits sequentially arrives at its data input.

Given input data = 1,1,0,1,0,0,1,1,0,1,0,1,1,0

Overlapping sequences detectable.

The below table shows the output for each sequence.

The output = 0,1,0,0,0,0,0,1,0,1,0,0

A D flip-flop is a type of flip-flop which uses two inputs, D (data) and a clock signal, to determine its output.

The output of a D flip-flop is the same as its input, D, when the clock signal is "low". When the clock signal is "high", the output of the flip-flop is the inverse of the logic level on the D input.

A negative edge-triggered D flip-flop is triggered when the clock signal goes from a high to a low state, thus causing the output of the flip-flop to change.

An asynchronous binary counter is a type of digital counter that is designed to count in binary sequences, but is not synchronized to an external clock source.

Unlike synchronous binary counters, asynchronous binary counters are not dependent on the clock and can change their output states at any point in time.

Asynchronous binary counters are most commonly used in applications that require a long sequence of counting with a wide range of timing options.

Propagation delay time in a flip flop is the time it takes for the output signal to change in response to a change in the input signal. It is determined by the speed of the flip flop circuit and is typically measured in nanoseconds.

Propagation delay time = 4 × 10ns = 40ns

The maximum clock frequency can be calculated using total propagation delay time: 1/t_p
= 1/40ns
= 25 MHz
Hence Option 3 is correct.

Concept:

For a counter with ‘n’ flip flops:

• The total number of states = 2ⁿ (0 to 2ⁿ – 1)
• The largest number that can be stored in the counter = 2ⁿ – 1
• To construct a counter with any MOD number, the minimum number of flip flops required must  satisfy: Modulus ≤ 2ⁿ
• Where n is the number of flip-flops and is the minimum value satisfying the above condition.
• Note: A MOD-N counter is also called as a divide by N counter as the input frequency is divided by the number of states of the counter.

Calculation:

Number no. of flip – flops are required to construct mod-12 counter,

must satisfy: 2ⁿ ≥ 12 The minimum value of n satisfying the above is: n = 4

Truth Table of JK flip flop

When both inputs are low, the next state output will be the present state output.

For J=0 & K=1, the next state output will always be 0 irrespective of the present state.

For J=1 & K=0, the next state output will always be 1 irrespective of the present state.

When both inputs are high, the next state output will be the complement of the present state output.

Characteristics table of JK flip flop

Excitation table of JK flip flop

From the excitation table, it is observed that:

If the present state is 0 and the next state is 1, then J = 1 & k = don't care.

Concept:
For a counter with ‘n’ flip flops:

• The total number of states = 2ⁿ (0 to 2ⁿ – 1)
• The largest number that can be stored in the counter = 2ⁿ – 1

To construct a counter with any MOD number, the minimum number flip flops required must satisfy:
Modulus ≤ 2ⁿ
Where n is the number of flip-flops and is the minimum value satisfying the above condition.

Calculation:
The total number of states required when n = 3:
2³  ≥  8
The states will vary from (0 to 7)
So the maximum states possible for the counter will be 8.

01111111 → 127
After 135 clock cycles, we will get
127 + 135 = 262
∴ The total number of clock pulses will be 262
As the modulus is 256,
After 256 clock pulses, the sequence will repeat.
262 = 256 + 6
∴ 00 00 00 00
257 → 00 00 00 01
258 → 00 00 00 10
259 → 00 00 00 11
260 → 00 00 01 00
261 → 00 00 01 01
262 → 00 00 01 10