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Test: Sequential Circuits - 1 - Electrical Engineering (EE) MCQ


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10 Questions MCQ Test Analog and Digital Electronics - Test: Sequential Circuits - 1

Test: Sequential Circuits - 1 for Electrical Engineering (EE) 2024 is part of Analog and Digital Electronics preparation. The Test: Sequential Circuits - 1 questions and answers have been prepared according to the Electrical Engineering (EE) exam syllabus.The Test: Sequential Circuits - 1 MCQs are made for Electrical Engineering (EE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Sequential Circuits - 1 below.
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Test: Sequential Circuits - 1 - Question 1

The expression for MOD number for a ripple counter with N flip-flops is

Detailed Solution for Test: Sequential Circuits - 1 - Question 1

Ripple Counter:

For a ripple counter if the number of flip flops is 'n' then total states are 2n and MOD is 2n 

BCD Counter:

A BCD counter counts 10 states from 0 to 9 

It is MOD 10 counter 

Number of flips required 4 

Ring counter:

A n bit ring counter counts n states and mod is "n"

Johnson Counter:

A n bit Johnson ring counter has 2n states and the mod is 2n

Test: Sequential Circuits - 1 - Question 2

Calculate the maximum clock frequency at which a 4-bit asynchronous counter can work reliably. Assume the propagation delay of each flip-flop to be 40 ns and the width of the strobe pulse to be 20 ns.

Detailed Solution for Test: Sequential Circuits - 1 - Question 2

Concept:

Lockout free condition: If a counter from an unused state enters one of the used states then the counter is called lock-out free. While taking any unused state as the initial state if the next state comes out to be a used state, the counter is said to be lockout free.

Synchronous counter: A counter in which all the flip-flops are triggered with the same clock pulse. In such counters, if the propagation delay of one flip-flop is tf, then the propagation delay for the whole counter will also be tf

Asynchronous counter: A counter in which all the flip flops are not triggered by the same clock pulse. In such counters, total propagation delay will be equal to the sum of propagation delay for all flip flops.

Calculation:

Given that, propagation delay of each flip-flop = 40 ns

Width of the strobe pulse = 20 ns

Total propagation delay = 40 × 4 + 20 = 180 ns

Maximum clock frequency

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Test: Sequential Circuits - 1 - Question 3

A cascade of three identical modulo-5 counters has an overall modulus of

Detailed Solution for Test: Sequential Circuits - 1 - Question 3

Concept:

Overall modulus of a cascaded system is the product of their individual modules.

For example:

A counter of modulus p, modulus q, and modulus r is cascaded, then the modulus of the overall counter is p × q × r

Calculation:

Given, 

The modulus of all three counters is 5

Then the overall modulus = 5 × 5 × 5 = 125

Test: Sequential Circuits - 1 - Question 4

A shift register with its complement output (Q’) of the last stage connected to the D-input of the first stage is called:

Detailed Solution for Test: Sequential Circuits - 1 - Question 4

Ring counter:

The Ring shift counter is a recirculating register in which the serial output is connected back to the serial input as shown:

 

A Straight ring counter with ‘n’ flip-flops will have n states.

Johnson counter:

A Johnson counter is a modified ring counter, where the inverted output from the last flip flop is connected to the input to the first.

It is also called a twisted ring counter.

The MOD of the Johnson counter is 2n if n flip-flops are used.

The circuit diagram for a 4-bit Johnson Counter is as shown:

Test: Sequential Circuits - 1 - Question 5

A 4-bit synchronous counter uses flip-flops with a propagation delay time of 15 ns each. The maximum possible time required for change of state will be 

Detailed Solution for Test: Sequential Circuits - 1 - Question 5

Concept:

The maximum propagation delay (tpd) for the synchronous counter is given by:

tpd = td

td = Propagation delay of 1 Flip flop.

Calculation:

Given is a 4-bit synchronous counter for which the maximum possible time needed for the change of state will be the maximum possible propagation delay:

tpd = Delay of 1 flip-flop only

tpd = 15 ns
Important Points

  • In synchronous counters, all flip-flops change simultaneously and in asynchronous counters, the propagation delay of the flip-flops add up to produce the overall delay.
  • Although synchronous counters usually have more combinational logic, the propagation delay through these gates is small compared to the propagation delay through many stages of flip-flops.
  • So the Synchronous counter will provide the least delay compared to Asynchronous counters.

The maximum propagation delay for an n-bit asynchronous counter is given by:

tpd = n × td

Test: Sequential Circuits - 1 - Question 6

If the input to a T flip-flop is a 100 MHz signal, the final output of three T flip-flops in a cascade is

Detailed Solution for Test: Sequential Circuits - 1 - Question 6

Concept:

If we pass the input signal to a single T-flip flop, we will get half of the frequency at the output.


Similarly, when we pass the input signal into an n-bit flip flop counter, the output frequency (fout) will be:

Application:

Given Input frequency f = 100 Hz

fout = 12.5 Hz

Test: Sequential Circuits - 1 - Question 7

A Shift register in which the output of the last flip-flop is connected to the input of the first flip-flop

Detailed Solution for Test: Sequential Circuits - 1 - Question 7

The Ring shift counter is a recirculating register in which the serial output is connected back to the serial input as shown:

A Straight ring counter with ‘n’ flip-flops will have n states.
Important Points
Johnson Counter:

A Johnson counter is a modified ring counter, where the inverted output from the last flip flop is connected to the input to the first.

The MOD of the Johnson counter is 2n if n flip-flops are used.

The circuit diagram for a 4-bit Johnson Counter is as shown:

Ripple Counter:

A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external clock.

All subsequent flip-flops are clocked by the output of the preceding flip-flop

Parallel Counter:

A parallel counter is a combinational logic circuit that receives a set of binary count signals in parallel and determines the final count after some fixed delay.

Test: Sequential Circuits - 1 - Question 8

A 6 bit counter is used to count from 0, 1, 2, ......n. The value of n is _____

Detailed Solution for Test: Sequential Circuits - 1 - Question 8

Concept:

A n bit counter has 2n states and can count from 0 to 2n-1

Application:

Given:

n = 6

so it will count from 0 to 26 - 1

= 0 to 63
Important Points

  • An n-bit ring counter has n states.
  • A Johnson counter has 2n states.
  • A ripple counter has 2n states.
Test: Sequential Circuits - 1 - Question 9

The sequence detected by the state diagram shown below is

Detailed Solution for Test: Sequential Circuits - 1 - Question 9

Pattern/Sequence detection:

To detect the sequence see only those i/p by which we can move in the forward direction.

 

Overlap/Non-Overlap:

We need to see the last state, after reaching the last state if we use bits of sequence then this will be overlapping, if we directly go to the initial state without using any bit then it will be non-overlapping.

In the question, we can see that at the last we will get sequence 1101101, 

we can use one bit in overlapping, but here we didn't use any bit of the previous detected sequence for detection of the next sequence so it is a non-overlapping type.

Test: Sequential Circuits - 1 - Question 10

Which one of the following statements is true about the digital circuit shown in the figure?

Detailed Solution for Test: Sequential Circuits - 1 - Question 10


From the given circuit diagram,


The output QA, QB, QC is repeating for every 5 clock pulses.

Hence frequency will be divided by 5.

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