Test: The Berkeley RISC Model & Digital Signal Processing - Computer Science Engineering (CSE) MCQ

Explanation: RISC 1 model is developed in the 1970s and uses a large register set of 138*32 bit. These are arranged in eight overlapping windows which have 24 registers each and these windows are split so that six registers can be used during function calls.

Explanation: The Berkeley RISC design was developed between the year 1980 and 1984 and later on the RISC design were commercialized as SPARC processor.

Explanation: The final design of RISC concept is called the RISC 1 which was published by ACM ISCA. It possesses 44500 transistors which can implement 31 instruction.

Explanation: The RISC 1 model have 78 registers of size 32 bits.

Explanation: RISC architecture is made for speeding up the processor with limited execution time whereas CISC architecture is mainly for code efficiency.

Explanation: When 8086 comes across any floating point arithmetic operations, it executes ESCAPE instruction code in order to pass the control of bus and instruction op-code to 8087.

Explanation: MMX instructions or multimedia extensions were introduced in Pentium processors to provide support for multimedia software running on a PC.

Explanation: Speculative execution is executed speculatively that is, following the predicted branch paths in the code until the true path is determined. If the processor executes correctly, then the performance is gained, if not, the results are discarded and the processor continues to execute until the correct path is identified.

Explanation: The ALU of DSP56000 have two 56-bit accumulator A and B each of which have small register with it.

Explanation: The ALU of DSP56000 have two 56-bit accumulator A and B each of which have small register with it.