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Computer Science Engineering (CSE) Exam  >  Computer Science Engineering (CSE) Tests  >  Embedded Systems (Web)  >  Test: The Sun SPARC RISC Model - Computer Science Engineering (CSE) MCQ

Test: The Sun SPARC RISC Model - Computer Science Engineering (CSE) MCQ


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10 Questions MCQ Test Embedded Systems (Web) - Test: The Sun SPARC RISC Model

Test: The Sun SPARC RISC Model for Computer Science Engineering (CSE) 2024 is part of Embedded Systems (Web) preparation. The Test: The Sun SPARC RISC Model questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: The Sun SPARC RISC Model MCQs are made for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: The Sun SPARC RISC Model below.
Solutions of Test: The Sun SPARC RISC Model questions in English are available as part of our Embedded Systems (Web) for Computer Science Engineering (CSE) & Test: The Sun SPARC RISC Model solutions in Hindi for Embedded Systems (Web) course. Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free. Attempt Test: The Sun SPARC RISC Model | 10 questions in 25 minutes | Mock test for Computer Science Engineering (CSE) preparation | Free important questions MCQ to study Embedded Systems (Web) for Computer Science Engineering (CSE) Exam | Download free PDF with solutions
Test: The Sun SPARC RISC Model - Question 1
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 What does SPARC stand for?

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Explanation: SPARC was designed for optimizing compilers and easily pipelined hardware implementations and it can license by anyone that is, having a nonproprietary architecture which is used to develop various microprocessors.

Test: The Sun SPARC RISC Model - Question 2
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How many bits does SPARC have?

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Explanation: It is a 32 bit RISC architecture having 32-bit wide register bank.

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Test: The Sun SPARC RISC Model - Question 3
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Which company developed SPARC?

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Explanation: SPARC is developed by Sun Microsystem but different manufacturers from other companies like Intel, Texas worked on it.

Test: The Sun SPARC RISC Model - Question 4
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What improves the context switching and parameter passing?
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Explanation: SPARC follows Berkeley architecture model and uses register windowing in order to improve the context switching and parameter passing. It also supports superscalar operations.

Test: The Sun SPARC RISC Model - Question 5
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 How many external interrupts does SPARC processor support?
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Explanation: SPARC processor provides 15 external interrupts which are generated by the interrupt lines IRL0-IRL3.

Test: The Sun SPARC RISC Model - Question 6
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Which level is an in-built nonmaskable interrupt in SPARC processor?
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Explanation: The level 15 of the SPARC processor is assigned to be a nonmaskable interrupt and the remaining 14 levels are unmasked and if necessary they can be made maskable.

Test: The Sun SPARC RISC Model - Question 7
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 How many instructions does SPARC processor have?
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Explanation: The instruction set of SPARC processor have 64 instructions which can be accessed by load and store operation with an RISC architecture.

Test: The Sun SPARC RISC Model - Question 8
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What is generated by an external interrupt in SPARC?
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Explanation: In SPARC when an external interrupt is generated, an internal trap is created in the trap base register in which the current and next instructions are saved, the pipeline gets flushed and the processor turns into a supervisor mode.

Test: The Sun SPARC RISC Model - Question 9
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 When an external interrupt is generated, what type of mode does the processor supports?
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Explanation: In SPARC when an external interrupt is called, it creates an internal trap in which the current and next instructions get saved and mode of the processor switches to supervisor mode.

Test: The Sun SPARC RISC Model - Question 10
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 Where is trap vector table located in SPARC processor?
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Explanation: The trap vector table is located in the trap base register which supplies the address of the service routine. When it is completed REIT instructions are executed.

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