Test: Noise Margin


10 Questions MCQ Test VLSI System Design | Test: Noise Margin


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This mock test of Test: Noise Margin for Electrical Engineering (EE) helps you for every Electrical Engineering (EE) entrance exam. This contains 10 Multiple Choice Questions for Electrical Engineering (EE) Test: Noise Margin (mcq) to study with solutions a complete question bank. The solved questions answers in this Test: Noise Margin quiz give you a good mix of easy questions and tough questions. Electrical Engineering (EE) students definitely take this Test: Noise Margin exercise for a better result in the exam. You can find other Test: Noise Margin extra questions, long questions & short questions for Electrical Engineering (EE) on EduRev as well by searching above.
QUESTION: 1

Noise Margin is :

Solution:

Noise Margin is defined as the amount of noise the logic circuit can withstand, it is given by difference between VOH and VIH or VIL and VOL.

QUESTION: 2

The VIL is found from transfer characteristic of inverter by:

Solution:

The VIL is the input voltage at which the slope of the transition will be equal to -1.

QUESTION: 3

The VIH is found from transfer characteristic of inverter by:

Solution:

The VIH is the input voltage at which the slope of the transition will be equal to -1. In Transfer characteristics at 2 points we will find the slope to be -1.

QUESTION: 4

The relation between threshold voltage and Noise Margin is:

Solution:

None.

QUESTION: 5

The Lower Noise Margin is given by:

Solution:

 Noise margin = VIL-VOL.

QUESTION: 6

The Higher Noise Margin is given by:

Solution:

Noise margin =VOH – VIH.

QUESTION: 7

The Uncertain or transition region is between:

Solution:

In Input the uncertain region is VIH and VIL.

QUESTION: 8

The noise immunity ____________ with noise margin

Solution:

The noise immunity is directly proportional to noise margin.

QUESTION: 9

If VIL of the 2nd gate is higher than VOL of the 1st gate, then logic output 0 from the 1st gate is considered as :

Solution:

 Logic output 0 from first gate is considered as logic input 0 at second gate as it lies within the range.

QUESTION: 10

If VIL of the 2nd gate is lower than VOL of the 1st gate, then logic output 0 from the 1st gate is considered as :

Solution:

The level of output signal from 1st gate is higher than the range for low input at 2nd gate. So it is uncertain.

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