Description

This mock test of Test: Electronic Devices - 5 for Electronics and Communication Engineering (ECE) helps you for every Electronics and Communication Engineering (ECE) entrance exam.
This contains 10 Multiple Choice Questions for Electronics and Communication Engineering (ECE) Test: Electronic Devices - 5 (mcq) to study with solutions a complete question bank.
The solved questions answers in this Test: Electronic Devices - 5 quiz give you a good mix of easy questions and tough questions. Electronics and Communication Engineering (ECE)
students definitely take this Test: Electronic Devices - 5 exercise for a better result in the exam. You can find other Test: Electronic Devices - 5 extra questions,
long questions & short questions for Electronics and Communication Engineering (ECE) on EduRev as well by searching above.

QUESTION: 1

The figure shows the VTC characteristics of an NMOS inverter with three varying resistive loads (R).

The correct statement is:

Solution:

- As V
_{i}is increased voltage drop across R_{L}increases and V_{0}decreases. - The sharpness of the transition region increases with the increasing load resistance.
- Hence
**R**_{3}> R_{2}> R_{1}.

*Answer can only contain numeric values

QUESTION: 2

Assume that the zero for electrostatic potential is in the semiconductor bulk at large x and that there is no metal semiconductor work function difference. The relative dielectric constant for the oxide is ϵ_{r} = 11.8. If the intrinsic concentration is 10^{10}/cm^{3}. The doping density N_{D} is _____ × 10^{17}/cm^{3} (KT = 0.026 V)

Solution:

The doping density is given by:

= 10^{10} e^{(0.437/0.026)}

= **1.99 × 10 ^{17}**

QUESTION: 3

The figure shows MOS capacitor variation with applied gate voltage for n-type body/substrate.

The flat band voltage is:

Solution:

- Flat band voltage is the voltage where there is no charge present in oxide or oxide-semiconductor interface. i.e. No thickness of channel
- C
_{ox}is constant and decreased subsequently

**Note:**Here, V_{G}is negative (for PMOS) - Hence, voltage is decreased from
**positive (V**._{FB}) to negative

*Answer can only contain numeric values

QUESTION: 4

The insulator capacitance C_{i} of an ideal MOS capacitor with 10-nm gate oxide (ε_{r} = 3.9) on p-type Si with N_{a} = 10^{16} cm^{-3} is ________ × 10^{-7} F/cm^{2}

Solution:

The insulator capacitance is the capacitance under strong accumulation

= 3.453 × 10^{-7} F/cm^{2}

QUESTION: 5

Which of the following curves represents the correct C – V characteristics of an NMOS transistor having an oxide layer thickness of 10 nm and a maximum depletion thickness of 100 nm. [Assume ϵ_{s} = permittivity of semiconductor, ϵ_{ox} = permittivity of oxide and

Solution:

Given, t_{ox }= 10 nm, d = 100 nm

C_{min} = series combination of C_{ox} and C_{dep
}

= **0.09 ϵA**

QUESTION: 6

The mobility of hole is 0.4 times the mobility of electron. What must be the ratio of width of n-channel to p-channel MOSFET if they are to have equal drain currents when operated in saturation mode with same magnitude of overdrive voltage:

Solution:

I_{D-n} = I_{D-p
}

μ_{n} W_{n} = μ_{p} W_{p
}

QUESTION: 7

The circuit shown uses an NMOS transistor to implement a current source. For the transistor V_{TN} = 1V and =12.5 uA/V^{2}. The required value of V_{GS} to get I_{DC} = 25 μA and corresponding compliance voltage is:

Solution:

2 = (V_{GS} - 1)^{2‑}

V_{GS} = √2 + 1 = **2.414 V**

To function as a current source, the transistor must be in saturation or V_{DS} > V_{DS} (sat).

V_{DS} (sat) = V_{GS} - V_{TN}

= 2.414 – 1

= 1.414.

Hence compliance voltage = **1.414 V.**

Compliance voltage is the minimum voltage required to achieve the desired performance.

*Answer can only contain numeric values

QUESTION: 8

The output resistance R_{0} of the NMOS circuit if I_{D} = 0.5 mA, λ = 0.02 V^{-1}, _____ kilo ohms.

Solution:

The small signal model with a test voltage V_{x} is shown.

The output resistance is given by:

From the circuit, V_{gs} = V_{x}

__Applying KCL:__

QUESTION: 9

For a MOSFET with gate plate area 0.5 × 10^{-2 }cm^{2} and oxide layer thickness 80 nm, the value of MOS capacitance and its break down voltage are: (assume relative di-electric constant of sio_{2}, ϵ_{r} = 4 and ϵ_{0} = 8.854 × 10^{-14} F/cm and dielectric strength of sio_{2} film is 5 × 10^{6} V/cm)

Solution:

Given gate plate area, which is also MOS capacitor area A = 0.5 × 10^{-2}cm^{2}

Oxide layer thickness t_{ox} = 80 nm

__The value of MOS capacitance:__

= **0.22 μF**

Dielectric breakdown happens of field greater than dielectric strength (5 × 10^{6} V/cm)

V = 5 × 10^{8} × 80 × 10^{-9} V =** 40V**

*Answer can only contain numeric values

QUESTION: 10

In the circuit shown in Figure, Transistors are characterized by and λ = 0

The output voltage V_{0} is _______V

Solution:

Gate is connected to drain Both Transistor are in Saturation.

__For M___{1}__ Transistor:__

⇒ (V - 8)^{2} = 4

⇒ V - 8 = ± 2

(i) Taking +ve, V = 8 + 2 = 10 V **(Not Possible)**

(ii) Taking -ve, V = 8 - 2 =** 6 V**

### Power Electronic Devices

Video | 07:22 min

### Opto Electronic Junction Devices

Doc | 4 Pages

### Revision Notes - Electronic Devices

Doc | 4 Pages

### Solved Examples - Electronic Devices

Doc | 2 Pages

- Test: Electronic Devices - 5
Test | 10 questions | 30 min

- Test: Electronic Devices & Circuits - 5
Test | 25 questions | 25 min

- Test: Electronic Devices - 3
Test | 10 questions | 30 min

- Test: Electronic Devices - 2
Test | 10 questions | 30 min

- Test: Electronic Devices - 2
Test | 20 questions | 60 min