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The correct answer is Electrically Erasable Programmable Read-Only Memory (EEPROM)
NOVRAM (Non-Volatile Random Access Memory):
The address bus width of a memory of size 1024 × 8 bits is
Concept:
The total memory can be calculated from the number of address lines and date-lines, i.e.
Total Memory = 2address lines × Data Lines
Calculation:
There are 1024 memory location
Now,
1024 = 210
Hence, the address bus width is 10 bits.
The data bus of 8 bits will be required to write/read data at each 8-bit memory location.
If the computer has 32 k words, then this memory unit has _______ memory locations.
Concept:
1 kB = 1024 bytes
One memory location of computer occupies 1 byte of memory.
So, to occupy 32 kB of memory = 32 × 1024 = 32768 bytes are required.
∵ 1 byte = 1 memory location
∴ 32 kB memory unit of computer will require 32768 memory locations.
A given memory chip has 14 address pins and 8 data pins. It has the following number of locations.
Concept:
Memory Chips:
Given that,
Address pins= 14 (is related to the number of memory locations)
Data pins= 8 (It is related to the size of the memory location)
So For 'N-Bits' address pins, the number of locations that will accommodate is 2N.
So For '14-Bits' address pins, the number of locations that will accommodate is 214.
Hence the correct answer is 214.
Cache Memory :
PLD’s (Programmable Logic Devices) are the circuits that contain an array of AND gates and another array of OR gates. There are three kinds of PLD’s depending upon the type of array, i.e.
ROM is a memory device that stores the binary information permanently.
Programmable Logic Arrays (PLA’s) implement two-level combination logic in sum-of-products (SOP) form.
PLA’s are Programmable AND array followed by Programmable OR array as shown:
PAL: Programmable AND array followed by fixed OR array
PROM:
Programmable logic array (PLA):
It is a kind of PLD (Programmable logic device) used to implement a combinational logic circuit.
1.It has a set of programmable AND gate planes which link a set of programmable OR gate planes.
Hence option (B) is the correct answer.
2.It has 2N AND Gate for N-input variable and form or Gates it has m output.
PLA Design:
The memory IC used in a digital system is selected or enabled only for the range of address assigned to it and this process is called memory decoding.
It denotes the memory to be selected for a specific address.
In an 8085 microprocessor, the number of address lines required to access a 16 K byte memory bank is
Concept:
An address line usually refers to a physical connection between a CPU and memory.
It specifies which address to access in the memory.
For an ‘n’ bit address line, we can access 2n memory locations.
Application:
Given, the number of memory locations = 16 kB
i.e. 2n = 16 kB
2n = 16 × 1 kB
2n = 24 × 210
2n = 214
So, n = 14 bits.