Test: Semiconductor Memories - 2 - Electronics and Communication Engineering (ECE)

The correct answer is Electrically Erasable Programmable Read-Only Memory (EEPROM)

• EEPROM stands for Electrically Erasable Programmable Read-Only Memory.
• It is a non-volatile memory in which the information stored Is retained even after the power goes off.
• A special type of PROM in which the information stored in it can be erased by exposing it to an electrical charge at one byte at a time. 
• EEPROM generally offers excellent capabilities and performance.
• EEPROMs are constructed as arrays of floating-gate transistors.

NOVRAM (Non-Volatile Random Access Memory):

• It is a type of memory that retains its contents when power is turned off.
• One type of NOVRAM is SRAM that is made non-volatile by connecting it to a constant power source such as a battery.
• Another type of NVRAM uses EEPROM chips to save its contents when power is turned off. In this case, NVRAM is composed of a combination of SRAM and EEPROM chips.

Concept:

The total memory can be calculated from the number of address lines and date-lines, i.e.

Total Memory = 2^{address lines} × Data Lines

Calculation:

There are 1024 memory location

Now,

 1024 = 2¹⁰

Hence, the address bus width is 10 bits.

The data bus of 8 bits will be required to write/read data at each 8-bit memory location.

Concept:

1 kB = 1024 bytes

One memory location of computer occupies 1 byte of memory.

So, to occupy 32 kB of memory = 32 × 1024 = 32768 bytes are required.

∵ 1 byte = 1 memory location

∴ 32 kB memory unit of computer will require 32768 memory locations.

Concept:

Memory Chips:

• The number of address pins is related to the number of memory locations.
• The data pins are typically bi-directional in read-write memories. The number of data pins is related to the size of the memory location.

Given that, 

Address pins= 14 (is related to the number of memory locations)

Data pins= 8 (It is related to the size of the memory location)

So For 'N-Bits' address pins, the number of locations that will accommodate is 2^N.

So For '14-Bits' address pins, the number of locations that will accommodate is 2¹⁴.

Hence the correct answer is 2¹⁴.

Cache Memory :

• Cache Memory is a special very high-speed memory.
• It is used to speed up and synchronizing with a high-speed CPU. Cache memory is costlier than main memory or disk memory but economical than CPU registers.
• Cache memory is an extremely fast memory type that acts as a buffer between RAM and the CPU.
• It holds frequently requested data and instructions so that they are immediately available to the CPU when needed.
• Cache memory is used to reduce the average time to access data from the Main memory.

PLD’s (Programmable Logic Devices) are the circuits that contain an array of AND gates and another array of OR gates. There are three kinds of PLD’s depending upon the type of array, i.e.

• Programmable Read-Only Memory
• Programmable Array Logic
• Programmable Logic Array (PLA)

• ROM is a memory device that stores the binary information permanently.

Programmable Logic Arrays (PLA’s) implement two-level combination logic in sum-of-products (SOP) form.

PLA’s are Programmable AND array followed by Programmable OR array as shown:

PAL: Programmable AND array followed by fixed OR array

PROM:

• It is known as programmable read-only memory
• It includes both AND array & OR array
• Out of these two arrays AND array is fixed and OR array is programmable.

Programmable logic array (PLA):

It is a kind of PLD (Programmable logic device) used to implement a combinational logic circuit.

1.It has a set of programmable AND gate planes which link a set of programmable OR gate planes.

Hence option (B) is the correct answer.

2.It has 2N AND Gate for N-input variable and form or Gates it has m output.

PLA Design:

The memory IC used in a digital system is selected or enabled only for the range of address assigned to it and this process is called memory decoding.

It denotes the memory to be selected for a specific address.

Concept:

An address line usually refers to a physical connection between a CPU and memory.

It specifies which address to access in the memory.

For an ‘n’ bit address line, we can access 2ⁿ memory locations.

Application:

Given, the number of memory locations = 16 kB

i.e. 2ⁿ = 16 kB

2ⁿ = 16 × 1 kB

2ⁿ = 2⁴ × 2¹⁰

2ⁿ = 2¹⁴

So, n = 14 bits.