Test: The PN - Junction

Due to cascading voltage gain

Voltage gain of 1^st satge

- Voltage gain of 2^nd stage
So it increases.
While upper cutoff frequency

While lower cutoff frequency

Increases compare to single state

As  decreases and  increases.

The gain of a transistor falls at high frequencies due to the various parasitic capacitances of the devices.

Input Resistance 
But overall input resistance seen from source is
R_IN = 10 || 10|| 5
R_IN = 2.5 kΩ.

The analysis will begin with the period t₁-t₂ of the input signal since the diode is in its short circuit state.

The output is across R, but it is also across 5 V battery so V₀ = 5V 
Applying KVL around the input loop
-20-5 + V_c = 0
V_c= 25 V

the capacitor will therefore charge up to 25 V from t₂ to t₃ the circuit will appear as shown below by applying KVL in the outside loop,
-10-25+V₀ =0
V₀ = 35 V
∴ The output waveform will be as

Here I_x =
But V_y = 

V_y = 11 V_x
I_x = (V_x - V_y) / (1M Ω)
  = (V_x - 11 V_x) / (10⁶ Ω) 
  = -10 V_x/ 10⁶
Therefore V_x / I_x = 10⁶/ (-10) = -100 K Ω

Assuming virtual ground,
V_m = V_A = 10V

Given is a depletion-type MOSFET. The drain current is given as,

When the n-channel between the two-doped regions is removed, it resembles an enhancement-type MOSFET as shown below.

For an enhancement-type MOSFET, 
Since, 
Thus, there is a 100% decrease in the drain current.

Equivalent circuit can be drawn with input voltage comparison and current feedback. It is shunt-shunt feedback.

The output voltage is across the series combination of 5 V supply, and the diode.
In the positive region of the input signal, the diode is an open circuit. The voltage drop across the resistor is zero. Hence,  There is a change in state at  Hence, the output is fixed at 5 V until , and above that the output waveform is same as the input waveform.
In the negative region of the input signal, the diode is on. When the diode is short-circuited, the output voltage is directly across the 5 V supply, and hence, the output is fixed at 5 V.
Hence, the output waveform is obtained as:

Since R_LOAD is infinite, we can replace with open circuit
C₁ will be charged in first +Ve half cycle
V_C1 = +5v
C₂ will be charged in first –Ve half cycle
V_C2 = -10v

When –0.7 V < Vi < 5.7 V output will following put, because zener diode and normal diodes are off
When Vi < –0.7 V Zener diode forward bias and V0 = –0.7 V
When Vi > 5.7 V Diode is forward bias and Vn = 5.7 V

If there is a small resistance added in the emitter of CE configuration will effect the gain as

   ⁼     

         ⁼  

  ⁼    

In the second case, the gain decreased due to emitter resistance R_E. as gain decreases , to maintain gain bandwidth product constant, bandwidth increases.

Given: V_CE(sat) = 0.2
V_BE = 0.7
β = 100
Writing KVL around the input loop
5 - I_BR_S - 0.7 = 0

Writing KVL around the output loop
5 - I_CR_C - V_CE = 0
V_CE = 5 - (0.215)R_C
For active region V_CE > V_CE(sat)
or,      V_CE > 0.2 V
So,     5 - 0.215R_C > 0.2
         0.215R_C < 5 - 0.2
Hence RC_(min) = 4.8 / (0.215) = 22.32 Ω 

If D₁ would have not been there then for V₁<0, D₂ ON and op-amp would have been in open loop mode.
In general Op-amp has high open loop gain which may cause the saturation.
By adding D₁ saturation is avoided.

The ac equivalent circuit for the network is given below.

The input impedance of the network is given as,

The transfer characteristics for an n-channel JFET when the controlling voltage, V_GS = 0V  is shown below.

It can be seen from the characteristics that when the voltage between the drain and source (V_DS) becomes greater than the pinch-off voltage (V_P), the drain current remains essentially the same, as the region between the two depletion regions will increase in length. The drain current I_D is fixed at the value I_D = I_DSS, where I_DSS is the maximum drain current.
Hence, the JFET acts as a current source as shown below, for V_GS = 0V, V_DS>V_p