10 Questions MCQ Test GATE Electrical Engineering (EE) 2024 Mock Test Series - Test: Logic Families - 1
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Option(1)- Schottky transistors are preferred for TTL logic systems. These transistors portray the Schottky effect and thus have higher switching speed in comparison to CMOS logic family.So option 1 is false. Option(2)- TTL dissipates a lot of power where as CMOS uses almost no power in the static state (that is, when inputs are not changing). So option 2 is false. Option(3)- TTL requires more space and isolation in comparison to CMOS logic family. The required silicon area for implementing CMOS is very small. So option 3 is true.
Figure of merit = Propagation Delay × Power Dissipation
For the best IC operation, FOM should be as small as possible.
Units: ns × mW
= pJ (pico Joule) Propagation delay (tpd):
tPHL = delay time in going form High to low logic
tPLH = Delay time in going from low to High logic Power dissipation (PD):
PD(avg) = Icc × Vcc
VCC = power supply
ICC = avg collector current calculated as the average of the High and low current, i.e.
The terms positive logic and negative logic refer to two conventions that tell the relationship between logical values and the voltages used to represent them.
Logic 0 is always used to represent false and logic 1 is always used to represent true in Boolean Algebra.
Positive Logic Convention:
In this, the more positive potential is considered to represent true or logic 1, and the more negative potential is considered to represent false or logic 0.
Negative Logic Convention:
In this, the more negative potential is considered to represent true or logic 1, and the more positive potential is considered to represent false or logic 0.
Two voltages are given -2 V and -1 V
As we have to represent them in the positive logic convention:
-2 V will represent logic 0 as it is more negative and
-1 V will represent logic 1.
Hence option (3) is the correct answer.
A TTL input signal is defined as "low" when between 0 V and 0.8 V with respect to the ground terminal.
A TTL input signal is defined as "high" when between 2 V and 5 V.
if a voltage signal ranging between 0.8 V and 2.0 V is sent into the input of a TTL gate, there is no certain response from the gate and therefore it is considered "uncertain" (precise logic levels vary slightly between sub-types and by temperature).
TTL outputs are typically restricted to narrower limits of between 0.0 V and 0.4 V for a "low".
TTL outputs are typically restricted to narrower limits of between 2.4 V and 5 V for a "high", providing at least 0.4 V of noise immunity.
The Transistor-Transistor Logic (TTL) is a logic family made up of BJTs (bipolar junction transistors).
The TTL family consists of various subfamilies such as standard TTL, low-power TTL, high power TTL, low power Schottky TTL, Schottky TTL, advanced low-power Schottky TTL, advanced Schottky TTL, and fast TTL.
The ICs which belong to the TTL family are designated as follows: 74 or 54 for standard TTL, 74L or 54L for low-power TTL, 74H or 54H for high power TTL, 74ALS or 54ALS for Low power Schottky TTL, and so on.
TTLs are available in different types and their classification is done based on the output like the following.
In a digital circuit, the Noise Margin is the amount by which the signal exceeds the threshold for a proper ‘0’ or ‘1’.
For Ex: a Digital circuit might be designed to swing between 0 and 1.2 Volts, with anything below 0.2 V considered as a ‘0’ and anything above 1 Volt is considered a ‘1’. Then the noise margin for a ‘0’ would be the amount that a signal is below 0.2 Volts, and a noise margin for 1 would be the amount by which a signal exceeds 1 Volt.
In this case noise margins are measured as an absolute voltage, not as a ratio.
This is schematically explained with the help of the following diagram:
A logic family is one of two related concepts: A logic family of monolithic digital integrated circuit devices is a group of electronic logic gates constructed using one of several different designs, usually with compatible logic levels and power supply characteristics within a family.
CMOS logic circuit is an extension of a CMOS inverter. It consists of two network transistors, a pull-down network (PDN) constructed of an n-MOS and Pull-up Network (PUN) constructed of P-MOS.
PDN: Since nMOS conducts when the signal gate is high, PDN is activated when the inputs are high. PUN: It comprises PMOS and conducts when the input signal gate is low.
The PDN and PUN are connected in parallel to form OR logic function and they are connected in series to form AND logic as shown:
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